Ángel López
García-Arias, Ph.D.

Research interests

• Deep learning, neural network architecture

• Digital design, computer architecture

• Non-linear systems, reservoir computing

• Telecommunications engineering

• Computational neuroscience

Experience

• 2024–        : NTT Communication Science Laboratories,
  Media Information Laboratory, Recognition Research Group
  Researcher

• 2021–24： Tokyo Institute of Technology, School of Engineering,
  AI Computing Research Unit (ArtIC  ·  Motomura Lab.)
  Ph.D. Engineering

• 2019–21： Osaka University, Graduate School of Information Science and Technology,
  Integrated System Design Laboratory (Former Hashimoto Lab.)
  Master's Degree, Information Science and Technology

• 2018–19： Same as above
  Research Student

• 2017–18： Autonomous University of Madrid, Engineering School,
  High Performance Computing and Networking research group
  Research Staff (Full-time)

• 2014–15： Osaka University, Engineering School,
  1 year exchange program: Immersion Exchange Program Osaka (iExPO)

• 2011–17： Autonomous University of Madrid, Engineering School
  Bach. Telecommunications Engineering
  (Major in Design and Implementation of Electronic Communication Systems)

Publications

First/Equal Contribution (*)

1. H. Otsuka*, D. Chijiwa*, Á. López García-Arias*, Y. Okoshi, K. Kawamura, T. Van Chu, D. Fujiki, S. Takeuchi, M. Motomura, "Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket," arXiv, 2024.

2. Á. López García-Arias, Y. Okoshi, M. Hashimoto, M. Motomura, and J. Yu,
   “Recurrent Residual Networks Contain Stronger Lottery Tickets,” IEEE Access, 2023.

3. Y. Okoshi*, Á. López García-Arias*, K. Hirose, K. Ando, K. Kawamura, T. Van Chu, M. Motomura, and J. Yu*,
   “Multicoated supermasks enhance hidden networks,” ICML, 2022. 

4. Á. López García-Arias, M. Hashimoto, M. Motomura, and J. Yu,
   “Hidden-fold networks: Random recurrent residuals using sparse supermasks,” BMVC, 2021.

5. Á. López García-Arias, J. Yu, and M. Hashimoto,
   “Low-cost reservoir computing using cellular automata and random forests,” ISCAS, 2020.

Secondary

1. H. Otsuka, Y. Okoshi, Á. López García-Arias, K. Kawamura, T. Van Chu, D. Fujiki, M. Motomura, "Restricted Random Pruning at Initialization for High Compression Range," TMLR, 2024.

2. J. Suzuki, J. Yu, M. Yasunaga, Á. López García-Arias, Y. Okoshi, S. Kumazawa, K. Ando, K. Kawamura, T. Van Chu, and M. Motomura, "Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision," IEEE Access, 2024.

3. H. Otsuka, Y. Okoshi, Á. López García-Arias, K. Kawamura, T. Van Chu, M. Motomura, “Ramanujan Edge-Popup: Finding Strong Lottery Tickets with Ramanujan Graph Properties for Efficient DNN Inference Execution,” SASIMI, 2024.

4. J. Yan, H. Ito, Á. López García-Arias, Y. Okoshi, H. Otsuka, K. Kawamura, T. Van Chu, and M. Motomura, “Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets”, LoG, 2023.

5. M. Hashimoto, Á. López García-Arias, J. Yu, "Bridging the Gap Between Reservoirs and Neural Networks," Photonic Neural Networks with Spatiotemporal Dynamics, Springer, 2023.

6. J. Suzuki, J. Yu, M. Yasunaga, Á. López García-Arias, Y. Okoshi, S. Kumazawa, K. Ando, K. Kawamura, T. Van Chu, and M. Motomura, “Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge,” VLSI Technology & Circuits, 2023.

7. K. Kawamura, J. Yu, D. Okonogi, S. Jimbo, G. Inoue, A. Hyodo, Á. López García-Arias, K. Ando, B. H. Fukushima-Kimura, R. Yasudo, T. V. Chu, M. Motomura, “Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension,” ISSCC, 2023.

8. K. Hirose, J. Yu, K. Ando, Y. Okoshi, Á. López García-Arias, J. Suzuki, T. V. Chu, K. Kawamura, and M. Motomura, “Hiddenite: 4K-PE hidden network inference 4D-tensor engine exploiting on-chip model construction achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet,” ISSCC, 2022.

9. Y. Okoshi, Á. López García-Arias, K. Hirose, K. Ando, K. Kawamura, T. Van Chu, M. Motomura, and J. Yu, “Strong Lottery Ticket Exploration for Hidden Neural Network Accelerator,” COOL Chips, 2022.

10. T. Alonso, M. Ruiz, Á. López García-Arias, G. Sutter, and J. E. López de Vergara, “Submicrosecond latency video compression in a low-end FPGA-based system-on-chip,” FPL, 2018.

Awards

• 2021: Award of the Graduate School of Information Science and Technology of Osaka University 

• 2018–2024: MEXT Scholar (Ministry of Education, Culture, Sports, Science and Technology, Japan)

Certifications

• Japanese Language Proficiency Test（JLPT）N1（2016）·  N2（2012）·  N3（2010）·  ４（2007）

• TOEIC: 985（2020）·  TOEFL: 105（2016）·  IGCSE（2009）

• Standard motor vehicle driver license (Japan, 2023)  ·  Standard two-wheel motor vehicle driver license (Japan, 2022）