Welcome to Li, Cong's Homepage

Biography

Cong Li is a principal engineer in Intel Asia-Pacific R&D Ltd. currently leading the middleware optimization for large-scale deep learning on GPUs or accelerators for datacenters and cloud environments. His recent interests lie in machine learning and data analytics approaches to runtime system management and optimization in various areas such as energy efficiency, reliability, and cluster performance/utilization. His work has been productized in multiple Intel software products including Intel® Data Center Manager, Intel® Memory Resilience Technology, Intel® Platform Resource Manager, etc. He has co-authored 20 papers and 2 book chapters in those areas, advancing the state of the art in memory reliability management (see, e.g., his papers in SC '22, ICCD '20 and '21), buffer cache replacement policies (see, e.g., his papers in Middleware '21, SYSTOR '18 and '19), performance management in cloud environments (see, e.g., his papers in IISWC '19 and '20, ISC '18), and system anomaly detection (see, e.g., his papers in ICDM '18, SEMI-THERM 32).  Before joining Intel in Sept. 2003, Cong had worked as an assistant researcher focusing on the research of natural language processing and machine learning for more than two years in Microsoft Research Asia where he published several papers on top level international conferences and journals with his major contribution to cross-task learning (see, e.g., his papers in ICML '03, ACL '02). He is also a part-time instructor in Children's Computer Center, Children's Palace of Chinese Welfare Institute in which he used to study computer technologies during his childhood, and now pays back with delivering various courses at weekends.

Last updated: Jan. 23rd, 2023