I am looking for Special Scholarship Program (SSP) Ph.D student!
SSP is the full-scholarship program in KUT. Please refer to the details of my program at below and the application guidance at our university page. Also, the introduction of our research topics may help you to figure out the fields we are focusing.
Master students are also welcome, but the financial support is decided on a case-by-case basis.
If you are interested, feel free to contact for more information.
Development of a method of observing the propagation of error inside ICs and its hardenning method
Integrated circuits (ICs) consist of numerous basic cells for computation. They are the core components of computers, which serve as the brains of the information society.
To support response to the explosively increasing demands for performance of computational tasks in applications such as artificial intelligence (AI), our laboratory is developing a method for observing the propagation of error inside existing systems for performing complex computation tasks. Based on our observations, we will establish a propagation model and estimate its error rate during the development of new IC designs or next generation ICs. Finally, we will develop a noise-hardening IC design for use in reliability-critical applications. (Refer to [1-4])
Moreover, for students with a strong interest in quantum computation for the post-CMOS IC era, we will provide further topics related to error correction against environmental noise, toward the realization of practical large-scale quantum computers. (Refer to [5])
Design and conduct simulations/experiments related to error injection for reliability analysis;
Develop an error propagation model and estimate the pre-fabrication error rate of pre-fabrication ICs; and
Design and verify high-reliability ICs, and optimize design for computation efficiency.
Work independently in accordance with the agreed research procedures;
Maintain good communication with team members; and
Have strong skills in English writing and presentation for academic purposes.
Self-motivation and strong interest in circuits;
Fluent English (necessary) and Japanese (preferred, related to collaboration in experiments);
Functional level of skill in use of software (C/C++, python etc.) and hardware (e.g., Verilog, VHDL) programming; and
Functional knowledge of VLSI.
[1] W. Liao et al., ‘Impact of the Angle of Incidence on Negative Muon-Induced SEU Cross Sections of 65-nm Bulk and FDSOI SRAMs’, IEEE Transactions on Nuclear Science, vol. 67, no. 7, pp. 1566–1572, 2020.
[2] W. Liao, K. Ito, S.-I. Abe, Y. Mitsuyama, and M. Hashimoto, ‘Characterizing Energetic Dependence of Low-Energy Neutron-Induced SEU and MCU and Its Influence on Estimation of Terrestrial SER in 65-nm Bulk SRAM’, IEEE Transactions on Nuclear Science, vol. 68, no. 6, pp. 1228–1234, 2021.
[3] T. Tanaka, W. Liao, M. Hashimoto, and Y. Mitsuyama, ‘Impact of Neutron-Induced SEU in FPGA CRAM on Image-Based Lane Tracking for Autonomous Driving: From Bit Upset to SEFI and Erroneous Behavior’, IEEE Transactions on Nuclear Science, vol. 69, no. 1, pp. 35–42, 2021.
[4] T.-S. Hsu, D.-A. Yang, W. Liao, M. Itoh, M. Hashimoto, and J.-J. Liou, ‘Processor SER Estimation with ACE Bit Analysis’, in 2021 21th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2021, pp. 1–5.
[5] W. Liao, Y. Suzuki, T. Tanimoto, Y. Ueno, and Y. Tokunaga, ‘WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code’, in Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023, pp. 209–215.