Implemented a UART transmitter and receiver on the Basys 3. Connected to a PC serial terminal (PuTTY) to verify end-to-end communication. The FPGA runs an echo design: PuTTY does not locally echo the keystrokes; it sends them to the board, and the FPGA immediately transmits the same bytes back, which is what you see appear in the terminal. This confirms correct start/stop framing, bit timing, and character handling. I implemented three separate modules for this lab: a UART Tx module, a UART Rx module, and a top module to connect the two. 

Implemented a synchronous mod-16 down counter that drives the seven-segment display from F to 0, then wraps back to F. A reset switch forces the counter to F at any time. Used the on-board clock with a clock divider to reach a human-readable update rate, then fed the 4-bit count into a 4-bit to 7-segment decoder (active-low segments). Single-digit enabled (no multiplexing) for a clean display.

Drove the Basys 3 seven-segment display using pure combinational logic, no clocked always @(posedge clk). A 4-bit input from the slide switches (binary-weighted 2^3...2^0) selects the digit to show. Implemented a 4-bit to 7-segment decoder that displays 0-9; any input larger than 9 is clamped to 0. Statically enabled a single digit (no display multiplexing), so 0000 = 0 and 1001 = 9, while values 1010–1111 also render 0 by design.