Algorithm & Chip

An analog-to-digital (A-to-D) conversion algorithm breaks through the speed limitation of the ADCs in advanced technology. The proposed A-to-D conversion algorithm utilizes the benefits of the speed-up techniques of sub-radix and multi-bit per cycle. We model the Vin-Vq transfer curves into linear equations with hardware-like parameters for in-depth analysis. The design constraints, guidelines, tradeoffs, and figure of merit (FoM) are provided for architecture optimization.

A calibration-free 13-bit 10 MS/s full-analog SAR ADC in 40 nm CMOS fully utilizes the timing and power budgets in a bit-conversion cycle by eliminating the digital circuits entirely. Continuous-time feedforward cascaded (CTFC) op-amps are proposed to enhance the residue power without the necessity of high precision quantizers. As opposed to the residue amplifiers (RAs) in multi-step/pipelined ADCs, the CTFC op-amps in open-loop configuration are implemented with the relaxing gain-bandwidth product (GBW) and without the limitations of accurate gain, precise settling, and voltage swing. Inverter-based regenerative amplifier (IRA) based zero-crossing detectors (ZCDs) with self-triggered amplification-to-regeneration (A-to-R) operation are developed to perform serial full-analog SAR bit conversions. The stability in multiple negative feedback (NFB) loops formed by the CTFC op-amps and ZCDs is analyzed and confirmed. The input-referred noise (IRN) and input-referred offset (IRO) in each bit conversion are suppressed by the CTFC op-amps and tolerated by the DAC radix and sub-ADC arrangements. The LSB repeating is adopted to entirely cancel out the suppressed IRO mismatches among the bit-conversions in the fine ADC. This work occupies an active area of 0.013 mm² and achieves the Nyquist-rate SNDR, SFDR, Walden FoM (FoMw), and Schreier FoM (FoM_S) of 67.6 dB, 77.2 dB, 3.3 fJ/conversion-step, and 176.5 dB, respectively.

A calibration-free 12-bit 50-MS/s full-analog SAR ADC in 40 nm CMOS integrates the functions of comparator, SAR logic, DAC switches into multiple feedback zero-crossing detectors (FB-ZCDs). By eliminating all the digital circuits, the full-analog bit-conversions operate with the asynchronous amplification-to-regeneration (A-to-R) operation that highly relaxes the requirements of the analog circuits and reference generator. This work is implemented without any calibration, where the non-ideal effects (offset mismatch, insufficient residue, and noise) are mitigated and eliminated with the proposed techniques as below. The offset mismatches among the FB-ZCDs are covered by the redundancies of the sub-radix DAC arrangement in the coarse ADC. Bottom-plate coupling compensators (BPCCs) are proposed to correct the consecutive SAR decision errors as quantizing the insufficient residue. The shared FB-ZCD with capacitor coupling decision (CCD) network is developed to obtain the identical offset in the fine ADC. Amplification extension (AE) technique is proposed to enhance the precision of the shared FB-ZCD by reconfiguring as a complementary inverter-based amplifier with the extended amplification period to enhance the output SNR. This work occupies an active area of 0.01 mm² and achieves the Nyquist-rate SNDR, SFDR, Walden FoM (FoM_W), and Schreier FoM (FoM_S) of 64.1 dB, 75.6 dB, 5.3 fJ/conversion-step, and 172.8 dB, respectively.

A 0.9 V 1.5 mW 150 MS/s 12-bit SAR ADC in 40 nm CMOS achieves a synergistic integration of multi-bit per cycle (M-bit/cycle) and sub-radix techniques with the comprehensive enhancement of speed and error tolerance. The proposed sub-radix-3 architecture uses a merged DAC with a two-input comparator instead of the conventional separated DACs (signal and reference DACs) with a four-input comparator to effectively improve the matching performance and power efficiency. Alternative-reference-switching (ARS) DACs are developed to reduce the total DAC effective switching capacitance by 47.4 %. Offset injection technique is implemented to calibrate the comparator offset without the speed and power penalty by eliminating the additional output loading of capacitor array or the extra input pair. The SAR logic of each conversion cycle is simplified into one single tri-latch current mode logic (CML) to directly control the DAC switches which effectively reduces the SAR delay by 2/3.

A 12-bit SAR ADC with segmented sub-radix-2 DAC and embedded digital calibration is implemented. The dither-based calibration with LMS adaptive filter is implemented to track the optimum bit-weights for compensation of DAC mismatch. Mid-threshold comparison switching procedure is proposed to tolerate both-side settling error by equalizing the up and down DAC transition voltage during SAR conversion.

An ultra-low-voltage and power-efficient 10-bit hybrid successive approximation register (SAR) analog-to-digital converter (ADC) is implemented. For reducing the digital-to-analog converter (DAC) capacitance and comparator requirement, we propose a hybrid architecture comprising a coarse 7-bit SAR ADC and fine 3.5-bit time-to-digital converter (TDC). The Vcm-based switching method is adopted for coarse conversion to reduce DAC power and maintain common mode. The residual voltage after coarse conversion is converted to time-domain, and the fine TDC detects the least three bits with 0.5-bit redundancy by using a Vernier delay structure. Offset calibration and delay time locking are implemented to guarantee the ADC performance under process variation.

Chronic obstructive pulmonary disease (COPD) still lacks a rapid diagnosis strategy. This chip is designed for implementation in a personal handheld device that detects patient breath for COPD diagnosis This chip is fabricated in 90 nm CMOS and consumes 1.68 mW at 0.5 V. The system distinguished between undiseased and diseased patients with 90.82% accuracy for a set of diseases including COPD and asthma and exhibited 92.31% accuracy for identifying patients with COPD or asthma. The system classified severity levels of COPD under four labels (normal, mild, moderate, and severe) with 92.00% accuracy. Accordingly, this work provides a promising solution for the unmet medical need of rapid COPD screening.

Ventilator-associated pneumonia (VAP) still lacks a rapid diagnostic strategy. This study proposes installing a noseon-a-chip at the proximal end of an expiratory circuit of a ventilator to monitor and to detect metabolite of pneumonia in the early stage. The nose-on-a-chip was designed and fabricated in a 90-nm 1P9M CMOS technology in order to downsize the gas detection system. This work provides a promising solution for the long-term unresolved rapid VAP diagnostic problem.