Research

Research Interest:

Novel device architectures for sub-10nm regime (Nanowire/Nanosheets)
Characterization and analytical compact modeling of low power devices (FDSOT, FinFETs etc.).
Energy efficient devices (NCFETs)

Ph.D Thesis:

Modeling of Substrate Depletion, Self-heating, Noise and High Frequency Effects in Fully Depleted SOI MOSFETs

Abstract: Fully Depleted Silicon on Insulator (FDSOI) is a planar process technology that has replaced bulk Si transistor in advanced CMOS process nodes. It has several benefits such as reduced short channel effects, immunity against random dopant fluctuation and threshold voltage tuning facility via back-bias. FDSOI has many inherent challenges due to its structure and some of key issues are self-heating, substrate depletion, higher flicker and substrate coupled thermal noise. As industry has opted FDSOI technology below 28 nm technology node, it is very important to come up with a computationally efficient compact model which can predict all above effects to exploit the benefits of FDSOI transistors. In this thesis, we have investigated the physics behind these effects and modeled them. All the developed models are validated with the state-of-the- art experimental data.

RF Model: Understanding the radio frequency behavior in the Fully depleted SOI (FDSOI) transistors, and determining the importance of parasitic networks at such high frequencies. Based on proposed theory, complete compact models for RF FDSOI and RF FinFET transistors are developed.

Link: P. Kushwaha, S. Khandelwal, J. P. Duarte, C. Hu and Y. S. Chauhan, "RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model," in IEEE Transactions on Microwave Theory and Techniques, vol. 64, no. 6, pp. 1745-1751, June 2016.doi: 10.1109/TMTT.2016.2557327

Thermal Model: To investigate the impact of geometrically scalable thermal resistance on the performance of FDSOI transistors.

Link: P. Kushwaha, S. Khandelwal, J. P. Duarte, C. Hu and Y. S. Chauhan, "RF Modeling of FDSOI Transistors Using Industry Standard BSIM-IMG Model," in IEEE Transactions on Microwave Theory and Techniques, vol. 64, no. 6, pp. 1745-1751, June 2016.doi: 10.1109/TMTT.2016.2557327

GAA Model: BSIM-CMG uni fied model can accurately model GAA FETs of different shapes including nanosheets, circular and non-circular wires and multi-bridge-channel FETs.

Link: P. Kushwaha, J.P. Duarte, Y-K. Lin, H. Agarwal, H-L. Chang, A. Sachid, S. Salahuddin, Y.S. Chauhan, C. Hu, “Unified Compact Model for Gate All Around FETs- Nanosheets, Nanowires, Multi Bridge Channel MOSFETs”, Workshop on Compact Modeling, Anaheim, CA, USA, 2018

Nanosheet and Nanowire FETs