Authors: Kobi Rappaport, Simcha Herschman

Goal: Implement an efficient convolutional layer on FPGA

Tools: Shoup's algorithm, MATLAB, Vivado-HLS , Xilinx Zedboard.

Result: An FPGA convolution implementation (4W) is x10 more power efficient than a Xeon CPU (50W). x5-x2 faster than CPU, when accounting for 2D inputs up to 150x150.

Year: 2018 | Source code

Authors: Bojun Ouyang, Leo Katz

Goal: Implement a Convolution Neural Network on FPGA

Tools: Tiled Convolution, Python, Tensorflow, MATLAB, Vivado-HLS , Xilinx Zedboard (Zynq-7000 chip).

Design Decisions: 16 bit fixed point representation for weights and activations, single pass (dataflow) memory access, double buffering for inter layer data flow.

Result: An HLS-based deep neural network design which is x25 more power efficient than a Nvidia GeForce 1070 GPU (50W). This compromised the inference time by a facctor of 2 and harmed the classification accuracy by less than 1%. Tested on CIFAR-10 image classification data-set.

Year: 2019