Research

AI technologies such as Convolutional Neural Network (CNN) have been utilized in many services related to our lives. One of the challenges of CNN execution is its high computation load which restricts using larger model in mobile and edge devices due to their tight power constraints. We have been studying on highly efficient CNN accelerator architectures and developed an LSI chip called SNACC (Scalable Neural Accelerator Cores with Cubic-integration). SNACC has TCI (Thru-Chip Interface) which is a wireless vertical interconnect technology to transmit signals between 3-D stacked chips with near field inductive coupling, allowing scalable core integration by stacking multiple SNACC chips.

Graph-based simultaneous localization and mapping (G-SLAM) fuses an important application, where mobile robots build a map of the environment while using it to locate Itself, to a ubiquitous data structure, graphs. It involves constructing graphs so that nodes are used to represent robot poses and landmarks while edges encode sensor measurements constraining connected poses. Solving it leads to minimization of errors between measurements and node configurations, which are compute- and memory-intensive. At Advanced Computing System Laboratory, we thrive to push its energy efficiency to foreseeable limits through hybrid precision support, mixed execution models and sparsity-aware operations with the help of multi-core processors, GPGPU and FPGA.

Path finding problem which try to find an appropriate path to the goal avoiding obstacles is one of the importation applications toward smart society. In real world, there are many moving obstacles (such as other cars for an autonomous driving car and human for a moving robot) around a target agent. Finding an effective path in such an environment is not an easy task since behavior of obstacles is sometimes unknown and there must be a huge number of candidate paths to go. We are researching on a Spiking Neural Network (SNN) algorithm for fast and low-power path planning in a many moving obstacles environment.

While AI technologies are applied to many applications, large amount of training data is necessary to achieve higher accuracy in inferences. Quality of sensor data obtained by edge devices are noisy and sometimes environment dependent which complicates to label them for constructing the training data set. We are working on on-device learning technologies using unsupervised learning technique which unnecessitate training data set for anomaly detection. We demonstrated its effectiveness in several target applications such as abnormal vibrations detection on fans, anomaly behavior detection in surveillance camera, and cyber security. This research has been conducted in collaboration with Matsutani Lab. in the same department.

Edge devices in the Internet of Things ecosystem generally have very stringent energy budgets that need to be managed efficiently. This is even more critical when these devices harness ambient energy from the environment as in the case of Energy Harvesting Wireless Sensor Nodes (EHWSNs). We are researching on automated techniques that leverage Reinforcement Learning (RL) to enable the edge devices to learn intelligent energy policies for long-term operation while maximizing performance.

Faced with insufficient resource provisioning of the portable terminals, edge computing is emerged as a novel location-aware paradigm to provide them with more processing capacity to improve the computing performance and quality of service (QoS) in several typical domains of human activity in smart society, such as social networks, medical diagnosis, telecommunications, recommendation systems, internal threat detection, transports, Internet of Things (IoT), and so on. These application domains often handle a vast collection of entities with various relationships, which can be naturally represented by the graph data structure. Graph processing is a powerful tool to model and optimize the complex problems based on this kind of data structure. We are conducting research on efficient architecture and edge-cloud cooperation for graph processing systems and its application to robot intelligence.

Quantum computers (QCs) are becoming an attractive computing paradigm as the number of implementable qubits increases. One of the challenges towards a rapid increase in the number of qubits is its high fragility of the quantum state due to decoherence and other noises, which necessitates error tolerance mechanisms. we are researching on quantum error collection (QEC) algorithm and its hardware implementation with superconducting digital circuit which is can operate in the cryogenic environment. The "on-line QEC algorithm" proposed by our research group performs a QCE process as soon as it detects qubit errors avoiding accumulation of uncorrected errors. Our scheme will contribute to the reduction of wiring between different temperature layers and be expected to increase scalability of future quantum computer systems.

Simulations using supercomputer systems have been widely utilized in many science and industrial field such as weather prediction, drug discovery, development of innovative design and production, and AI technologies. For more advanced and larger scale simulations, further performance improvement of supercomputers is indispensable. Towards development the next-generation system of "supercomputer Fugaku", we are investigating advanced technologies and explore the possible architectures with application and system co-design.This research is conducted as a part of research effort as the next-generation high-performance architecture research team of RIKEN center for computational science.