Kim Hazelwood, Ph.D.

Kim Hazelwood is an engineering manager in Facebook’s Infrastructure division, where she leads a performance analysis and hardware-software co-design team. Her research interests include datacenter server architectures, optimizing compilers, workload characterization, dynamic binary translation, and applied machine learning. Prior to Facebook, Kim held positions including a tenured Associate Professor at the University of Virginia, Research Scientist at Intel, Software Engineer at Google, and Director of Systems Research at Yahoo Labs. She received a PhD in Computer Science from Harvard University in 2004.

Honors & Awards.

• Board of Directors, Computing Research Association, 2017-2020.
• ACM SIGPLAN Most Influential PLDI Paper Award (10-Year Test of Time Award), 2015.
• Promoted to Associate Professor (with tenure) effective August 25, 2011.
• Buy My Book on Amazon! Dynamic Binary Modification: Tools, Techniques, and Applications, 2011.
• Top 35 Innovators under 35, MIT Technology Review, 2010.
• NASA New Investigator Award, Virginia Space Grant Consortium, 2010.
• Anita Borg Early Career Award, Computing Research Association, 2009.
• Career Enhancement Fellowship, Woodrow Wilson National Fellowship Foundation, 2008.
• CAREER Award, National Science Foundation, 2007.
• FEST Distinguished Young Investigator Award, Fund for Excellence in Science and Technology, 2007.

Publications.

Svilen Kanev, Juan Pablo Darago, Kim Hazelwood, Parthasarthy Ranganathan, Tipp Moselely, Gu-Yeon Wei, and David Brooks. "Profiling a Warehouse-Scale Computer.," International Symposium on Computer Architecture (ISCA), June 2015.

Svilen Kanev, Kim Hazelwood, Gu-Yeon Wei, and David Brooks. "Tradeoffs between Power Management and Tail Latency in Warehouse-Scale Applications," IEEE International Symposium on Workload Characterization (IISWC), October 2014.

Apala Guha, Kim Hazelwood, and Mary Lou Soffa. "Memory Optimization of Dynamic Binary Translators for Embedded Systems,"Transactions on Architecture and Code Optimization (TACO), Volume 9, Issue 3, September 2012.

Chris Gregg, Jonathan Dorn, Kim Hazelwood, and Kevin Skadron. "Fine-Grained Resource Sharing for Concurrent GPGPU Kernels,"4th USENIX Workshop on Hot Topics in Parallelism (HotPar). Berkeley, CA. June 2012.

Michelle McDaniel and Kim Hazelwood. "Runtime Adaptation: A Case for Reactive Code Alignment," Proceedings of the 2nd International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era (Exadapt). London, UK. March 2012.

Chris Gregg, Luther Tychonievich, Kim Hazelwood, James Cohoon. "Parallel Programming in Elementary School," Proceedings of the 43rd ACM Technical Symposium on Computer Science Education. Raleigh, NC. February 2012.

Kim Hazelwood. "Process-Level Virtualization for Runtime Adaptation of Embedded Software," 48th ACM/EDAC/IEEE Design Automation Conference (DAC). San Diego, CA. June 2011.

Chris Gregg, Michael Boyer, Kim Hazelwood, and Kevin Skadron. "Dynamic Heterogeneous Scheduling Decisions Using Historical Runtime Data," Proceedings of the 2nd Workshop on Applications for Multi- and Many-Core Processors. San Jose, CA. June 2011.

Chris Gregg and Kim Hazelwood. "Where is the Data? Why You Cannot Debate GPU vs. CPU Performance Without the Answer,"International Symposium on Performance Analysis of Systems and Software (ISPASS). Austin, TX. April 2011.

Dan Upton and Kim Hazelwood. "Finding Cool Code: An Analysis of Source-Level Causes of Temperature Effects," International Symposium on Performance Analysis of Systems and Software (ISPASS). Austin, TX. April 2011.

Michelle McDaniel and Kim Hazelwood. "Performance Characterization of Mobile-Class Nodes: Why Fewer Bits is Better,"International Symposium on Performance Analysis of Systems and Software (ISPASS). Austin, TX. April 2011.

Yair Lifshitz, Robert Cohn, Inbal Livni, Omer Tabach, Mark Charney, and Kim Hazelwood. "Zsim: A Fast Architectural Simulator for ISA Design-Space Exploration," 3rd Workshop on Infrastructures for Software/Hardware Co-Design(WISH-3). Chamonix, France. April 2011.

Perhaad Mistry, Chris Gregg, Norman Rubin, David Kaeli, and Kim Hazelwood. "Analyzing Program Flow within a Many-Kernel OpenCL Application," 4th Workshop on General Purpose Processing on Graphics Processing Units (GPGPU-4). Newport Beach, CA. March 2011.

Derek Davis and Kim Hazelwood. "Improving Region Selection through Loop Completion," ASPLOS Workshop on Runtime Environments/Systems, Layering, and Virtualized Environments (RESoLVE). Newport Beach, CA. March 2011.

Balaji Dhanasekaran and Kim Hazelwood. "Improving Indirect Branch Translation in Dynamic Binary Translators," ASPLOS Workshop on Runtime Environments/Systems, Layering, and Virtualized Environments (RESoLVE). Newport Beach, CA. March 2011.

Apala Guha, Kim Hazelwood, Mary Lou Soffa. "Balancing Memory and Performance through Selective Flushing of Software Code Caches," International Symposium on Compilers Architectures and Synthesis for Embedded Systems (CASES). Scottsdale, AZ. October 2010, pages 1-10. Best Paper Nominee!

Vijay Janapa Reddi, Simone Campanoni, Meeta S. Gupta, Kim Hazelwood, Michael D. Smith, Gu-Yeon Wei, and David Brooks. "Eliminating Voltage Emergencies via Software-Guided Code Transformations," Transactions on Architecture and Code Optimization (TACO), Volume 7, Issue 2, September 2010.

Dan Upton and Kim Hazelwood. "Design of a Custom VEE Core in a Chip Multiprocessor," 6th IEEE Symposium on Application Specific Processors (SASP). Anaheim, CA. June 2010.

Chris Gregg, Jeff Brantley, and Kim Hazelwood. "Contention-Aware Scheduling of Parallel Code for Heterogeneous Systems," 2nd USENIX Workshop on Hot Topics in Parallelism (HotPar). Berkeley, CA. June 2010.

Alex Skaletsky, Tevi Devor, Nadav Chachmon, Robert Cohn, Kim Hazelwood, Vladimir Vladimirov, Moshe Bach. "Dynamic Program Analysis of Microsoft Windows Applications," International Symposium on Performance Analysis of Software and Systems (ISPASS). White Plains, NY. April 2010, pages 2-12. Acceptance Rate: 34%.

Apala Guha, Kim Hazelwood, Mary Lou Soffa. "DBT Path Selection for Holistic Memory Efficiency and Performance," ACM/USENIX International Conference on Virtual Execution Environments (VEE). Pittsburgh, PA. March 2010, pages 145-156. Acceptance Rate: 27%.

Moshe Bach, Mark Charney, Robert Cohn, Tevi Devor, Elena Demikovsky, Kim Hazelwood, Aamer Jaleel, Chi-Keung Luk, Gail Lyons, Harish Patil, Ady Tal. "Analyzing Parallel Programs with Pin," IEEE Computer. March 2010, vol. 43, no. 3, pages 34-41. Cover Feature!

Dan Upton, Kim Hazelwood, Greg Lueck, and Robert Cohn. "Improving Instrumentation Speed via Buffering," Workshop on Binary Instrumentation and Applications (WBIA). December 2009, pages 52-61.

Mojtaba Mehrara, Thomas Jablin, Dan Upton, David August, Kim Hazelwood, and Scott Mahlke. "Compilation Strategies and Challenges for Multicore Signal Processing," IEEE Signal Processing Magazine (IEEE SPM). Volume 26, Issue 6, November 2009, page 55-63.

Marisabel Guevara, Chris Gregg, Kim Hazelwood, Kevin Skadron. "Enabling Task Parallelism in the CUDA Scheduler," in Proceedings of the Workshop on Programming Models for Emerging Architectures (PMEA). Raleigh, NC. September 2009, pages 69-76.

Daniel Williams, Aprotim Sanyal, Dan Upton, Jason Mars, Sudeep Ghosh, and Kim Hazelwood. "A Cross-Layer Approach to Heterogeneity and Reliability," Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE). Cambridge, MA, USA. July 2009, pages 88-97. Acceptance Rate: 35%.

Kim Hazelwood, Greg Lueck, and Robert Cohn. "Scalable Support for Multithreaded Applications on Dynamic Binary Instrumentation Systems," Proceedings of the 2009 International Symposium on Memory Management (ISMM). Dublin, Ireland. June 2009, pages 20-29. Acceptance Rate: 46%.

Kim Hazelwood and Mohamed Zahran. "Challenges and Opportunities at All Levels: Interactions Among Operating Systems, Compilers, and Multicore Processors," ACM SIGOPS Operating System Review. Volume 43, Issue 2. April 2009.

Arkaitz Ruiz-Alvarez and Kim Hazelwood. "Evaluating the Impact of Dynamic Binary Translation Systems on Hardware Cache Performance," in Proceedings of the IEEE International Symposium on Workload Characterization (IISWC). Seattle, Washington, USA. September 2008. Acceptance Rate: 34%.

Jason Mars, Daniel Williams, Dan Upton, Sudeep Ghosh, Kim Hazelwood. "A Reactive, Unobtrusive Prefetcher for Multicore and Manycore Architectures," in Proceedings of the Workshop on Software and Hardware Challenges of Manycore Platforms (SHCMP). Beijing, China. June 2008.

Apala Guha, Kim Hazelwood, Mary Lou Soffa. "Code Lifetime Based Memory Reduction for Virtual Execution Environments," inProceedings of the 6th Workshop on Optimizations for DSP and Embedded Systems (ODES). Boston, Massachusetts, USA. April 2008.

Duane Merrill and Kim Hazelwood. "Trace Fragment Selection within Method-Based JVMs," in in Proceedings of the 2008 Annual ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE). Seattle, Washington, USA. March 2008, pages 41-50. Acceptance Rate: 32%.

Steven Wallace and Kim Hazelwood. "SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance," in Proceedings of the 5th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO-5). Palo Alto, California, USA. March 2007, pages 209-217. Best Paper Runner-Up! Acceptance Rate: 32%.

Apala Guha, Jason D. Hiser, Naveen Kumar, Jing Yang, Min Zhao, Shukang Zhou, Bruce R. Childers, Jack W. Davidson, Kim Hazelwood, Mary Lou Soffa. "Virtual Execution Environments: Support and Tools," in Proceedings of the NSF Next Generation Software Program Workshop held in conjunction with the International Parallel and Distributed Processing Symposium. Long Beach, California, USA. March 2007, pages 1-6.

Dan Upton and Kim Hazelwood. "Heterogeneous Chip Multiprocessor Design for Virtual Machines," in Proceedings of the Workshop on Software Tools for Multicore Systems held in conjunction with the 5th Annual IEEE/ACM International Symposium on Code Generation and Optimization. Palo Alto, California, USA. March 2007, pages 44-47.

Apala Guha, Kim Hazelwood, Mary Lou Soffa. "Reducing Exit Stub Memory Consumption in Code Caches," in Proceedings of the International Conference on High Performance Embedded Architectures and Compilers (HiPEAC). Ghent, Belgium. January 2007, pages 87-101. Acceptance Rate: 29%.

Kim Hazelwood and Artur Klauser. "A Dynamic Binary Instrumentation Engine for the ARM Architecture," in Proceedings of the 2006 ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES). Seoul, Korea. October 2006, pages 261-270. Acceptance Rate: 41%.

Kim Hazelwood and Michael D. Smith. "Managing Bounded Code Caches in Dynamic Binary Optimization Systems," Transactions on Architecture and Code Optimization (TACO), Volume 3, Issue 3, September 2006, pages 263-294.

Kim Hazelwood and Robert Cohn. "A Cross-Architectural Framework for Code Cache Manipulation," in Proceedings of the 4th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO-4). Manhattan, New York, USA. March 2006, pages 17-27. Acceptance Rate: 35% (26/75).

David Hiniker, Kim Hazelwood, Michael D. Smith. "Improving Region Selection in Dynamic Optimization Systems," in Proceedings of the 38th Annual International Symposium on Microarchitecture (MICRO-38). Barcelona, Spain. November 2005, pages 141-154. Acceptance Rate: 20% (29/147).

Chi-Keung Luk, Robert Cohn, Robert Muth, Harish Patil, Artur Klauser, Geoff Lowney, Steven Wallace, Vijay Janapa Reddi, Kim Hazelwood. "Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation," in Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation (PLDI). Chicago, Illinois, USA. June 2005, pages 191-200. Acceptance Rate: 21%.

Kim Hazelwood and David Brooks. "Eliminating Voltage Emergencies via Microarchitectural Voltage Control Feedback and Dynamic Optimization," in Proceedings of the 2004 ACM International Symposium on Low-Power Electronics and Design. Newport Beach, California, USA. August 2004, pages 326-331. Acceptance Rate: 34%.

Kim Hazelwood and James E. Smith. "Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems," inProceedings of the Second Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO-2). Palo Alto, California, USA. March 2004, pages 89-99. Awarded Best Presentation! Acceptance Rate: 32%.

Kim Hazelwood and Michael D. Smith. "Generational Cache Management of Code Traces in Dynamic Optimization Systems," inProceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-36). San Diego, California, USA. December 2003, pages 169-179. Acceptance Rate: 26%.

Kim Hazelwood and Michael D. Smith. "Characterizing Inter-Execution and Inter-Application Optimization Persistence," inProceedings of the Workshop on Exploring the Trace Space for Dynamic Optimization Techniques held in conjunction with the 17th Annual ACM International Conference on Supercomputing. San Francisco, California, USA. June 2003, pages 51-58.

Kim Hazelwood and David Grove. "Adaptive Online Context-Sensitive Inlining," in Proceedings of the First Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO-1). San Francisco, California, USA. March 2003, pages 253-264. Acceptance Rate: 35%.

Kim Hazelwood and Michael D. Smith. "Code Cache Management Schemes for Dynamic Optimizers," in Proceedings of the Sixth Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-6) held in conjunction with the Eighth Annual International Symposium on High-Performance Computer Architecture (HPCA-8). Boston, Massachusetts, USA. February 2002, pages 102-110.

Kim Hazelwood, Mark Toburen and Thomas Conte. "A Case for Exploiting Memory-Access Peristence," in Proceedings of the 2001 Workshop on Memory Performance Issues held in conjunction with the 28th Annual International Symposium on Computer Architecture (ISCA-28). Göteborg, Sweden. June 2001.

Kim Hazelwood and Thomas Conte. "A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization," inProceedings of the 2000 ACM International Conference on Parallel Architectures and Compilation Techniques. Philadelphia, Pennsylvania, USA. October 2000, pages 71-80. Acceptance Rate: 21% (22/107)

Kim Hazelwood, Walter Ligon, Greg Monn, Natasha Pothen, Ron Sass, Dan Stanzione, and Keith Underwood. "Creating Applications in RCADE," in Proceedings of the IEEE Aerospace Conference, Volume 2. Aspen, Colorado. IEEE Computer Society Press. March 1999, pages 337-349.

Brian Boysen, Nathan DeBardeleben, Kim Hazelwood, Walter Ligon, Ron Sass, Dan Stanzione, and Keith Underwood. "A Development Environment for Configurable Computing," in SPIE 3526: Configurable Computing Technology and Applications, Bellingham, Washington, USA. November 1998, pages 103-112.