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Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms
Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms
Kevin Chang, Abdullah Giray Yaglikci, Saugata Ghose, Abhijith Kashyap, Hasan Hassan, Aditya Agrawal, Niladrish Chatterjee, Donghyuk Lee, Mike O’Connor, Onur Mutlu. In SIGMETRICS, Jun. 2017.
chang_sigmetrics17.pdfkevin_chang_sigmetrics_2017.pptxSoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies
SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies
Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, Onur Mutlu. In HPCA, Feb. 2017.
softMC_hpca17.pdfUnderstanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization
Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization
Kevin Chang, Abhijith Kashyap, Hasan Hassan Samira Khan, Kevin Hsieh, Donghyuk Lee, Saugata Ghose, Gennady Pekhimenko, Tianshi Li, Onur Mutlu. In SIGMETRICS, Jun. 2016.
chang_sigmetrics16.pdfchang_SIGMETRICS_2016.pptxLow-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM
Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM
Kevin Chang, Prashant J. Nair, Donghyuk Lee, Saugata Ghose, Moinuddin K. Qureshi, Onur Mutlu. In HPCA, Mar. 2016.
kchang_lisa_hpca2016.pdfchang_hpca2016_lisa.pptxDASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators
DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators
Hiroyuki Usui, Lavanya Subramanian, Kevin Chang, Onur Mutlu. In TACO, Jan. 2016.
dash_deadline-aware-heterogeneous-memory-scheduler_taco16.pdfAdaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case
Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Khan, Vivek Seshadri, Kevin Chang, Onur Mutlu. In HPCA, Feb. 2015.
Design and Evaluation of Hierarchical Rings with Deflection Routing
Design and Evaluation of Hierarchical Rings with Deflection Routing
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu. In SBAC-PAD, Oct. 2014.
hierarchical-rings-with-deflection_sbacpad14.pdfImproving DRAM Performance by Parallelizing Refreshes with Accesses
Improving DRAM Performance by Parallelizing Refreshes with Accesses
Kevin Chang, Donghyuk Lee, Zeshan Chishti, Alaa Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu. In HPCA, Feb. 2014.
chang_hpca2014.pdfchang_hpca2014_talk_public.pptxBufferless and Minimally-Buffered Deflection Routing
Bufferless and Minimally-Buffered Deflection Routing
Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Chang, Rachata Ausavarungnirun, Onur Mutlu. Invited Chapter in Routing Algorithms in Networks-on-Chip, pp. 241-275, Springer, 2014.
HAT: Heterogeneous Adaptive Throttling for On-Chip Networks
HAT: Heterogeneous Adaptive Throttling for On-Chip Networks
Kevin Chang, Rachata Ausavarungnirun, Chris Fallin, Onur Mutlu. In SBAC-PAD, Oct. 2012.
sbacpad2012_hat.pdfchang_sbacpad12_talk.pptxStaged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems
Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems
Rachata Ausavarungnirun, Kevin Chang, Lavanya Subramanian, Gabriel H. Loh, Onur Mutlu. In ISCA, Jun. 2012.
MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect
MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect
Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Chang, Rachata Ausavarungnirun, Onur Mutlu. In NOCS, 2012.
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