Last Update: 25.09.03

Kent Edrian Lozada

Post-Doctoral Researcher @ KAIST

AFFILIATION

KAIST

kjlozada@kaist.ac.kr

LOCATION

Daejeon, Korea

Complete CV

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💭 ABOUT ME

I am currently a postdoctoral researcher at the KAIST Mixed-Signal Integrated Circuits Laboratory (MSICL) (msicl.kaist.ac.kr) under the 2025 KAIST Jang Young Sil Fellow Program (Excellence Track).

I received my Ph.D. in electrical engineering from KAIST in 2025 under the supervision of Professor Seung-Tak Ryu. My research interests focus on mixed-signal integrated circuit design with an emphasis on data converters. I worked on high-resolution and low-power analog-to-digital converters (ADCs), continuous-time (CT) and hybrid ADCs (e.g., SAR-assisted ADCs), and delta–sigma modulators (DSMs).

During my M.S.-Ph.D. studies, I focused on developing a high-resolution, low-power, digital-intensive ADC architecture. Specifically, I worked on a digital-intensive SAR-assisted CT DSM architecture, which offers significant advantages over discrete-time (DT) ADCs, such as inherent anti-aliasing and ease of driving. The emphasis on digital-intensive stems from their robustness to PVT variations, flexibility, and, more importantly, scalability, allowing them to fully leverage digital-friendly advanced process nodes.

My contributions have been widely recognized at numerous top-tier IEEE conferences and journals, including the IEEE Symposium on VLSI Technology and Circuits (VLSI Circuits), IEEE Custom Integrated Circuits Conference (CICC), IEEE Journal of Solid-State Circuits (JSSC), etc. I have also received numerous paper invitations, presentation opportunities, and several awards.

🎓 EDUCATION

Korea Advanced Institute of Science and Technology (KAIST)

Sep. 2019 - Feb. 2025

Integrated M.S. - Ph.D. in Electrical Engineering (Advisor: Prof. Seung-Tak Ryu)

Dissertation Title: Design of Digital-Intensive Continuous-Time Delta-Sigma Modulator Architecture

Recipient of 2025 KAIST College of Engineering Outstanding Ph.D. Dissertation Award [Full List]

University of the Philippines Los Baños (UPLB)

May 2012 - Jan. 2018

B.S. in Electrical Engineering Major in Electronics Engineering (5-Year Curriculum)

💻 WORK / RESEARCH EXPERIENCES

Post-Doctoral Researcher

Mar. 2025 - Present

Recipient of 2025 KAIST Jang Young Sil Fellow Program (Excellence Track)

KAIST, School of Electrical Engineering (Supervisor: Prof. Seung-Tak Ryu)

Mixed-Signal Integrated Circuits Laboratory (MSICL)

Graduate Student Research Assistant

Sep. 2019 - Feb. 2025

KAIST, School of Electrical Engineering (Supervisor: Prof. Seung-Tak Ryu)

Mixed-Signal Integrated Circuits Laboratory (MSICL)

Instructor II

Apr. 2018 - Jul. 2019

UPLB, Department of Electrical Engineering

🔎 RESEARCH HIGHLIGHTS

1. A Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS (VLSI Circuits 2024 / JSSC 2025)

In this research, we proposed a digital-intensive, single-opamp, 4th-order CT DSM architecture with a simple and low-power 3rd-order SAR-assisted digital noise-coupling (DNC). To overcome the challenges associated with the limited order of noise coupling (NC), a digital back-end integrator is employed, achieving a maximum stable amplitude (MSA) of − 1.6 dBFS even with aggressive noise shaping in a single-loop design. A digital adder-free 3rd-order DNC filter is introduced to eliminate the need for digital adders previously required in the DNC filter. By successfully implementing a 3rd-order NC filter (and through delay cells alone), this work achieves the highest-order NC filter reported to date.

2. A Single-Opamp Third-Order SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator Digital Noise Coupling in 28-nm CMOS (A-SSCC 2023 / JSSC 2024)

In this research, we proposed a single-opamp 3rd-order SAR-assisted CT 1-0 MASH DSM incorporating a 2nd-order DNC. By leveraging the strengths of DNC and MASH, this combination effectively addresses inherent limitations, enhancing the system’s overall performance. The proposed dual-loop MASH design simplifies the architecture by implementing the first-stage ADC and second-stage ADC into a single SAR ADC. This eliminates the necessity for accurate quantization extraction, removing any timing matching or dedicated residue amplification, typically required in conventional CT MASH. The second-stage quantization error goes through the DNC path and is injected back into the first-stage quantizer input, providing additional noise-shaping.

3. A Fourth-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling in 28-nm CMOS (TCAS-II 2022)

In this research, we proposed a hybrid noise-coupling (HNC) technique to mitigate the issues with a DNC structure. In the proposed technique, the unwanted quantization noise that is generated from the noise-coupling ADC is injected into the input of the quantizer with one-clock cycle delay, thus increasing the order of noise shaping of this error. Behavioral simulation shows that the HNC is highly robust against gain variation. The proposed 4th-order CT DSM with HNC scheme was designed in a 28-nm CMOS technology. With an oversampling ratio (OSR) of 32, the proposed design achieves a SNDR of 97.20-dB at a signal bandwidth of 15.625-kHz, which has a 7-dB improvement in comparison to DNC only without introducing significant hardware complexity.

📒 JOURNAL PUBLICATIONS & CONFERENCE PROCEEDINGS

FIRST AUTHOR (JOURNAL)

1. A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS

Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, and Seung-Tak Ryu
IEEE Journal of Solid-State Circuits (JSSC) 2025 (Invited Paper: Special Issue for VLSI Circuits 2024) [Paper]

2. SAR-Assisted Energy-Efficient Hybrid ADCs

Kent Edrian Lozada, Dong-Jin Chang, Dong-Ryeol Oh, Min-Jae Seo, and Seung-Tak Ryu
IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) 2024 (Invited Paper: Tutorial Review Paper) [Paper]

3. A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator with Digital Noise Coupling

Dong-Hun Lee‡, Kent Edrian Lozada‡ (‡ Equal Contribution), Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, and Seung-Tak Ryu
IEEE Journal of Solid-State Circuits (JSSC) 2024 (Invited Paper: Special Issue for A-SSCC 2023) [Paper]

4. A 4th-Order Continuous-Time Delta-Sigma Modulator with Hybrid Noise-Coupling

Kent Edrian Lozada, Il-Hoon Jang, Gyeom-Je Bae, Dong-Hun Lee, Ye-Dam Kim, Hankyu Lee, Seong Joong Kim, and Seung-Tak Ryu)
IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II) 2022 (Invited Paper: Special Issue for MWSCAS 2022) [Paper]

FIRST AUTHOR (CONFERENCE)

5. Continuous-Time Delta-Sigma Modulator with SAR-Assisted Digital Noise Coupling

Kent Edrian Lozada, Ye-Dam Kim, Il-Hoon Jang, and Seung-Tak Ryu
IEEE Custom Integrated Circuits Conference (CICC) 2025 (Invited Paper: Tutorial Review Paper) [Paper]
(Nominated for Best Invited Paper)

6. A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-order Continuous-Time Delta-Sigma Modulator with 3rd-order Noise Coupling

Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, and Seung-Tak Ryu
IEEE Symposium on VLSI Technology and Circuits (VLSI Circuits) 2024 [Paper]

7. A 25kHz-BW 97.4dB-SNDR 100.2-DR 3rd-order SAR-Assisted CT DSM with 1-0 MASH and DNC

Kent Edrian Lozada‡, Dong-Hun Lee‡ (‡ Equal Contribution), Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, and Seung-Tak Ryu
IEEE Custom Integrated Circuits Conference (CICC) 2024 (Invited Presentation: Special Session for A-SSCC 2023 Best Student Papers)

8. A 25kHz-BW 97.4dB-SNDR 100.2-DR 3rd-order SAR-Assisted CT DSM with 1-0 MASH and DNC

Kent Edrian Lozada‡, Dong-Hun Lee‡ (‡ Equal Contribution), Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, and Seung-Tak Ryu
IEEE Asian Solid-State Circuits Conference (A-SSCC) 2023 [Paper]

9. A 4th-Order Continuous-Time Delta-Sigma Modulator with Hybrid Noise-Coupling

Kent Edrian Lozada, Il-Hoon Jang, Gyeom-Je Bae, Dong-Hun Lee, Ye-Dam Kim, Hankyu Lee, Seong Joong Kim, and Seung-Tak Ryu)
IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 2022 (Presentation only; Invited and published directly to IEEE TCAS-II)

CO AUTHOR (BOTH JOURNAL & CONFERENCE)

10. A 160kHz-BW 96.7dB-SNDR Two-Step 2-1 MASH Hybrid Incremental ΔΣ ADC with Automatic Inter-Stage Gain Selection

Kwan-Hoon Song, Young-Hun Moon, Kun-Woo Park, Kent Edrian Lozada, Seung-Tak Ryu
IEEE Asian Solid-State Circuits Conference (A-SSCC) 2025 (Accepted, to be presented in Nov. 2025)

11. A 184dB-FoMS 25kHz-BW 98.6dB-SNDR Fully Dynamic Discrete-Time Delta-Sigma Modulator with Digital Noise Coupling

Young-Hun Moon, Kun-Woo Park, Kwan-Hoon Song, Kent Edrian Lozada, Min-Jae Seo, and Seung-Tak Ryu
IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 2025

12. A 10-kHz BW 97-dB SNDR 3rd-Order Incremental Delta-Sigma ADC with Hybrid CT/DT Loop Filter

Kwan-Hoon Song, Kun-Woo Park, Young-Hun Moon, Kent Edrian Lozada, and Seung-Tak Ryu
IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 2025

13. DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs with Digital Input-Interference Cancellation

Lizhen Zhang, Bo Gao, Kun-Woo Park, Kent Edrian Lozada, Raymond Mabilangan, Hyeongjin Kim, Jianhui Wu, and Seung-Tak Ryu
IEEE Open Journal of Circuits and Systems (OJCAS) 2024 [Paper]

14. A 5x OSR 1MHz-BW 81dB-SNDR 5th-Order Noise-Shaping SAR ADC with Zero-Optimized 3rd-Order Integrator

Lizhen Zhang, Bo Gao, Kun-Woo Park, Hyeongjin Kim, Kent Edrian Lozada, Ye-Dam Kim, Juanhui Wu, and Seung-Tak Ryu
IEEE Asian Solid-State Circuits Conference (A-SSCC) 2024 [Paper]

15. TID-Tolerant StrongARM Comparator and Sampling Network for Satellite Application High-Voltage ADCs

Charlie Tahar, Changyeop Lee, Kun-Woo Park, Kent Edrian Lozada, Hyojun Kim, Ki-Ho Kwon, and Seung-Tak Ryu
IEEE Asian Solid-State Circuits Conference (A-SSCC) 2024 [Paper]

16. A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA

Bo Gao, Lizhen Zhang, Raymond Mabilangan, Chang-Un Park, Kent Edrian Lozada, Ho-Jin Kim, Youngjae Cho, Michael Choi, and Seung-Tak Ryu
IEEE Asian Solid-State Circuits Conference (A-SSCC) 2024 [Paper]

17. A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF

Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Chang-Un Park, Kun-Woo Park, Kwan-Hoon Song, Young-Hoon Moon, Min-Jae Seo, and Seung-Tak Ryu
IEEE Symposium on VLSI Technology and Circuits (VLSI Circuits) 2024 [Paper]

18. A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization

Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Dong-Jin Chang, and Seung-Tak Ryu
IEEE Asian Solid-State Circuits Conference (A-SSCC) 2021 [Paper]

📒 PATENTS (INTERNATIONAL & DOMESTIC)

INTERNATIONAL

1. Amplification Apparatus, Integration Apparatus and Modulation Apparatus Each Including Duty-Cycled Resistor

Wonseok Lee, Kent Edrian Lozada, Seung Tak Ryu, and Sang Joon Kim
US11916523 (Granted, February 2024) [Link]

2. Converter with Improved Signal-to-Noise Ratio and Method of Operation of the Same

Hojin Kim, Kent Edrian Lozada, Donghun Lee, Seung Tak Ryu, Heewok Shin, Youngjae Cho, and Michael Choi
US0202493 (Published, June 2025) [Link]

2. Digital Noise Coupling Circuit and Continuous-Time Modulator Including the Same

Seong Joong Kim, Seung Tak Ryu, and Kent Edrian Lozada
US0146322 (Published, May 2024) [Link]

4. Continuous-Time Operation Amplifier and Operating Method

Seong Joong Kim, Seung Tak Ryu, and Kent Edrian Lozada
US0120895 (Published, April 2024) [Link]

DOMESTIC

5. 컨버터 및 컨버터의 동작 방법
김호진, 켄트 에드리안 로자다, 이동훈, 류승탁, 신희욱, 조영재, 최병주
KR10-2025-0090940 (Published, June 2025) [Link]

6. 디지털 노이즈 커플링 회로 및 디지털 노이즈 커플링 회로를 포함하는 연속 시간 변조기

김성중, 류승탁, 로자다 켄트
KR10-2024-0062384 (Published, May 2024) [Link]

7. 연속 시간 연산 증폭기 및 그 동작 방법

김성중, 류승탁, 로자다 켄트
KR10-2024-0050062 (Published, April 2024) [Link]

8. 듀티 사이클 저항을 포함하는 증폭 장치, 적분 장치 및 변조 장치
이원석, 켄트 에드리안 로자다, 류승탁, 김상준
KR10-2022-0050658 (Published, April 2022) [Link]

📚 REVIEWER SERVICE (BOOKS, JOURNALS, CONFERENCES)

Analysis and Design of Data Converters by Behzad Razavi, Cambridge University Press
2025
IEEE Journal of Solid-State Circuits (JSSC)
2025
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
2024, 2025

IEEE Open Journal of Circuits and Systems (OJCAS)
2024
IEEE Transactions on Very Large Scale Integration (TVLSI)
2025
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
2025
MDPI Sensors (Sensors)
2025

🏆 HONORS, AWARDS, GRANTS, & FELLOWSHIP (SELECTED ONLY)

KAIST Jang Young Sil Fellow Program 2025
KAIST, Office of Research Affairs

Outstanding Ph.D. Dissertation Award 2025
KAIST, College of Engineering

IEEE SSCS Student Travel Grant 2024
IEEE CICC 2024
Distinguished Design Award 2023
IEEE A-SSCC Student Design Contest

Excellence Award 2021
IITP-ITRC KAIST AISS Workshop

KAIST Scholarship 2019
Integrated M.S. - Ph.D. Program

💡 OTHERS

Languages
Filipino (Native), English (Native), and Korean (Basic)

Software, Programming Languages, & EDA Tools
C/C++, MATLAB (Including Simulink), PCAD and/or Altium Designer (Basic PCB Design), LaTeX (Document Typesetting), OriginLab (Data Plotting), and Cadence Virtuoso (Full-Custom IC Design)

CMOS Process
180 nm, 28 nm

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