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COMPUTER ORGANIZATION
COMPUTER ORGANIZATION
COURSE CONTENT
COURSE CONTENT
Course Content:
Course Content:
Syllabus Overview - [ SYLLABUS ]
UNIT - 1
UNIT - 1
Syllabus:
Syllabus:
Digital Computers and Arithmetic:
Digital Computers and Arithmetic:
Historical perspective and von Neumann computers, Fixed and floating-point representation of numbers, Addition and Subtraction, Multiplication and Division algorithms, Floating-point arithmetic operations.
Historical perspective and von Neumann computers, Fixed and floating-point representation of numbers, Addition and Subtraction, Multiplication and Division algorithms, Floating-point arithmetic operations.
Neumann computers-[ PPT ] - [ VIDEO ]
Fixed point representation- [ PPT ] - [ VIDEO ] [ VIDEO ]
Floating point representation of numbers - [ PPT ] - [ VIDEO ] [VIDEO ]
Addition and Subtraction algorithms - [ PPT ] - [ VIDEO-1 ] [ VIDEO-2 ] [ VIDEO ] [ VIDEO ]
UNIT - 2
UNIT - 2
SYLLABUS:
SYLLABUS:
Basic Computer Organization and Design:
Basic Computer Organization and Design:
Instruction Codes, Computer Registers, Computer Instructions, Timing and Control, Instruction Cycle, Memory-Reference Instructions, Input Output and Interrupt, Complete Computer Description, Design of Basic Computer.
Instruction Codes, Computer Registers, Computer Instructions, Timing and Control, Instruction Cycle, Memory-Reference Instructions, Input Output and Interrupt, Complete Computer Description, Design of Basic Computer.
Micro programmed Control: Control Memory, Address Sequencing, Micro program Example, Design of Control Unit
Micro programmed Control: Control Memory, Address Sequencing, Micro program Example, Design of Control Unit
Instruction codes -[ PPT ] - [ VIDEO ]
Computer Registers -[ PPT ] - [ VIDEO ] - [ VIDEO ]
Register transfer - [PPT ] - [ VIDEO ]
Computer instructions -[ PPT ] - [ VIDEO-1 ] - [VIDEO-2 ] [ VIDEO ]
Timing and Control -[ PPT ] - [ VIDEO] - [ VIDEO ]
Instruction cycle -[ PPT ] - [ VIDEO ]
Memory- Reference instruction -[ PPT] - [ VIDEO ]
Register Reference - [VIDEO ]
Input Output Interrupt - [ VIDEO ]
Input Output reference Instruction -[ PPT ] - [ VIDEO ]
Design of Basic Computer -[ PPT ] - [ VIDEO ]
Micro programmed control -[ PPT ] [ PPT ] [ VIDEO ] [ VIDEO ] [ VIDEO ] [ VIDEO ]
Control memory - [ VIDEO ]
UNIT - 3
UNIT - 3
SYLLABUS:
SYLLABUS:
Central Processing Unit:
Central Processing Unit:
Introduction, General Register Organization, Stack Organization, Instruction Formats, Addressing Modes, Data Transfer and Manipulation, Program Control, Reduced Instruction Set Computer(RISC)
Introduction, General Register Organization, Stack Organization, Instruction Formats, Addressing Modes, Data Transfer and Manipulation, Program Control, Reduced Instruction Set Computer(RISC)
Notes - [ PPT ]
General Register Organization -[ PPT ] - [ VIDEO ]
Stack Organization - [ PPT ] - [ VIDEO ] [ VIDEO ] [ VIDEO ] [ VIDEO ]
Instruction Formats - [ PPT ] - [ VIDEO ]
Addressing Modes -[ PPT ] - [ VIDEO ] - [ EXAMPLE ]
Data Transfer - [ PPT ] - [ VIDEO ] [ VIDEO ]
Data Manipulation - [ VIDEO ] [ VIDEO ] [ VIDEO ]
Program control - [ VIDEO ]
UNIT - 4
UNIT - 4
SYLLABUS:
SYLLABUS:
Memory and I/O Organization:
Memory and I/O Organization:
Memory Hierarchy, Associative Memory, Cache Memory, Virtual memory. I/O Organization: Peripheral devices, I/O interface, Asynchronous data transfer, Modes of transfer, Priority interrupt, direct memory access and IOP
Memory Hierarchy, Associative Memory, Cache Memory, Virtual memory. I/O Organization: Peripheral devices, I/O interface, Asynchronous data transfer, Modes of transfer, Priority interrupt, direct memory access and IOP
[ MATERIAL ] [ MATERIAL - 1 ] [ MATERIAL - 2 ]
Main memory - [ VIDEO ]
Peripheral devices - [ PPT ] [ PPT ] [ PPT ]
UNIT - 5
UNIT - 5
UNIT - 5
UNIT - 5
SYLLABUS:
SYLLABUS:
Pipeline and Vector Processing:
Pipeline and Vector Processing:
Parallel Processing, Pipelining, Arithmetic and Instruction Pipelines, RISK Pipeline, Vector Processing, Array Processors. Multiprocessors, Interconnection structures, Cache coherence.
Parallel Processing, Pipelining, Arithmetic and Instruction Pipelines, RISK Pipeline, Vector Processing, Array Processors. Multiprocessors, Interconnection structures, Cache coherence.
ASSIGNMENTS
ASSIGNMENTS
FIRST ASSIGNMENT
SECOND ASSIGNMENT
QUESTION PAPERS
QUESTION PAPERS
MID 1
MID 2
CLASS TEST
SEMESTER
MARKS
MARKS
MID - 1 , 2 and Sessionals
ATTENDANCE
ATTENDANCE
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