Collaborators:
Saurabh Singh, Indian Institute of Information Technology Guwahati
Vishesh Mishra, Indian Institute of Information Technology Guwahati
Divy Pandey, Indian Institute of Information Technology Guwahati
Sagar Satapathy, Indian Institute of Technology Jodhpur
The project is guided by:
Dip Sankar Banerjee, Indian Institute of Technology Jodhpur
Approximate computing offers the flexibility to trade-off accuracy for computational speed, reduced power consumption, and smaller on-chip area. Approximation techniques are extensively employed in the design of approximate arithmetic circuits such as adders and multipliers. Although several approximate adder designs have been proposed in the past, there exists scope for further improvement. Existing state-of-the-art designs often involve a trade-off between the margin of acceptable error and its Quality of Results(QoR). In this paper, we propose an approximate adder with relatively higher accuracy while accommodating hardware constraints simultaneously. We name the proposed adder as an efficient reconfigurable carry speculative approximate adder with rectification, or simply EFCSA adder. Additionally, we propose another variant of the EFCSA adder called REFCSA, which is inherently reconfigurable in nature, allowing accuracy configuration during runtime. The proposed design aims at limiting the length of the carry chain in the conventional ripple carry adder (RCA) using a block-based mechanism. Further, we have also proposed a rectification scheme to modify the error-prone sum bits at various locations. Our adder showcases results that are 12.3x faster than the conventional RCA. On average, our adder is 45.1% more accurate and has 31.97% better power-delay-product (PDP) than several existing state-of-the-art approximate designs.
Collaborators:
Divyansh Singh Maura, Indian Institute of Information Technology Guwahati
Tanmay Goel, Indian Institute of Information Technology Guwahati
The project is guided by:
Dip Sankar Banerjee, Indian Institute of Technology Jodhpur
Shirshendu Das, Indian Institute of Technology Ropar
In the midst of progressively shrinking silicon technologies, enhancements in performance and area requirements come at the cost of some side effects. One such cost is the deviation of nominal parameters of process, voltage, and temperature. Considered a manufacturing defect, variations limit the maximum achievable performance. These affected areas possess lower reliability and consume more power than their theoretical counterpart.
In this paper, we study and mitigate variations observed in GDDRx based GPU memories. GPU devices are exploited primarily for their massive parallelism and applications with both regular and irregular memory accesses see significant performance benefits. We also find that these consume a significant portion of the total GPU power. We propose a variation mitigating and power-saving technique for GPU memories. This accounts for a power savings of up to 44.61% (20.3% on average). Simultaneously, we also maintain the device data which prevents page faults and re-computation costs. This, however, leads to some performance overheads, which are limited to 4%. Mitigation of process variation combined with state preservation leads to more reliable GPU computations. Additionally, our model lowers access latencies by 15.7% in comparison to a variation affected baseline GPU, which ultimately helps to improve the throughput of the device.
The project is guided by:
Hemanta Kumar Mondal, National Institute of Technology Durgapur
Shirshendu Das, Indian Institute of Technology Ropar
Dip Sankar Banerjee, Indian Institute of Technology Jodhpur
Dynamic Random Access Memory (DRAM) is the de-facto choice for main-memories due to its cost-effectiveness. It offers larger capacity and higher bandwidth compared to SRAM but is slower than the latter. With each passing generation, DRAMs are becoming denser. One of its side-effects is the deviation of nominal parameters: process, voltage, and, temperature. DRAMs are often considered as the bottleneck of the system as it trades off performance over-capacity. With such inherent limitations, further deviation from nominal specifications is undesired. In this paper, we investigate the impact of variations in conventional DRAM devices on the aspects of performance, reliability, and energy requirements. Based on this study, we model a variation-aware framework, called VAR-DRAM, which can be integrated with any modern-day DRAM type. It provides enhanced power management by taking variations into account. VAR-DRAM ensures faster execution of programs as it internally remaps data from variation affected cells to normal cells and also ensures data preservation. On extensive experimentation, we find that VAR-DRAM achieves peak energy savings of up to 48.8% with an average of 29.54% on DDR4 memories while improving the access latency of the DRAM compared to a variation affected device by 7.4%.
The project is guided by:
Dip Sankar Banerjee, Indian Institute of Technology Jodhpur
Shirshendu Das, Indian Institute of Technology Ropar
In recent years, DRAM-based main memories have become susceptible to the Row Hammer (RH) problem, which causes bits to flip in a row without accessing them directly. Frequent activation of a row, called an aggressor row, causes its adjacent rows’ (victim) bits to flip. The state-of-the-art solution is to refresh the victim rows explicitly to prevent bit flipping. There have been several proposals made to detect RH attacks. These include both probabilistic as well as deterministic counter-based methods. The technique of handling RH attacks, however, remains the same. In this work, we propose an efficient technique for handling the RH problem. We show that the mechanism is agnostic of the detection mechanism. Our RH handling technique omits the necessity of refreshing the victim rows. Instead, we use a small non-volatile Spin-Transfer Torque Magnetic Random Access Memory (STTRAM) which ensures no unnecessary refreshes of the victim rows on the DRAM device and thus allowing more time for normal applications in the same DRAM device. Our model relies on the migration of the aggressor rows. This accounts for removing blocking of the DRAM operations due to the refreshing of victim rows incurred in the previous solution. After extensive evaluation, we found that, compared to the conventional RH mitigation techniques, our model minimizes the blocking time of the memory which is imposed due to explicit refreshing by an average of 80.72% in the worst case scenario and provides energy savings of about 15.82% on average, across different types of RH based workloads. A lookup table is necessary to pinpoint the location of a particular row, which, when combined with the STTMRAM, limits the storage overhead to 0.39% of a 2 GB DRAM. Our proposed model prevents repeated refreshing of the same victim rows in different refreshing windows on the DRAM device and leads to an efficient RH handling technique.
Collaborators:
Divyansh Singh Maura, Indian Institute of Information Technology Guwahati
Tanmay Goel, Indian Institute of Information Technology Guwahati
The project is guided by:
Dip Sankar Banerjee, Indian Institute of Technology Jodhpur
Shirshendu Das, Indian Institute of Technology Ropar
Dynamic Random Access Memory (DRAM) is the \textit{de-facto} choice for main memories in modern-day computing systems. It is based on capacitor technology, which is volatile in nature. Hence, these memories require periodic refreshing, usually at 64 ms, in order to ensure data persistence. Refreshing results in blocking of the memory device for performing normal read or write operations. However, it has been found that not all cells of the device require uniform refreshing at 64 ms. Due to the shrinking of technologies, deviations are observed in nominal parameters which cause variations in retention and restoration time.
In this paper, we propose a retention-aware DRAM refreshing model, which is operated in auto-refresh (AR) mode of a DRAM device. We call the proposed model Lightweight Retention Time-Aware Refreshing, or simply LRAR, which can be operated either in a deterministic or an approximate mode while consuming a constant amount of hardware space. The former ensures consumption of the least possible area in comparison to previously proposed works. While the latter is aimed to incorporate periodic refreshing for a newly emerged DRAM phenomenon called Variable Retention Time, or, VRT, which uses the basics of approximation. After extensive evaluation, we find that our proposed model reduces the execution time of programs up to 11% (9.4% on average). The memory system's energy consumption is also reduced by an average of 11.5%, and refresh energy by an average of 73.6%. We achieve the aforementioned gains at a modest area overhead of 7,240 um^2 (0.0018% of a 400 mm^2 die) and storage overhead.
Collaborators:
Shobhit Belwal, Indian Institute of Information Technology Guwahati
Rajat Bhattacharjya, Indian Institute of Information Technology Guwahati
The project is guided by:
Dip Sankar Banerjee, Indian Institute of Technology Jodhpur
Approximate computing in recent times has emerged as a popular alternative to conventional computing techniques. Fault-tolerant applications in the domains of machine learning, signal processing, and computer vision have shown promising results using approximate computing. Approximations on adders and multipliers have been widely proposed in literature and innovations on that front are still a necessity so as to target specific applications. In this paper, an approximate carry-lookahead adder (ACLA) is proposed which makes use of an intelligent approach for judging the carry of subsequent stages. Also, a correction mechanism is proposed so as to hinder substantial accuracy loss. Experimental results show that ACLA is faster than the traditional ripple-carry adder by 70.5% for 32-bit configurations on an average. In terms of accuracy, for 32-bit configurations, ACLA outperforms other state-of-the-art adders such as SARA and BCSA by 51%.
Collaborators:
Rajat Bhattacharjya, Indian Institute of Information Technology Guwahati
Vishesh Mishra, Indian Institute of Information Technology Guwahati
Saurabh Singh, Indian Institute of Information Technology Guwahati
The project is guided by:
Dip Sankar Banerjee, Indian Institute of Technology Jodhpur
Approximate computing has in recent times found significant applications towards lowering power, area, and time requirements for arithmetic operations. Several works done in recent years have furthered approximate computing along these directions. In this work, we propose a new approximate adder that employs a carry prediction method. This allows parallel propagation of the carry allowing faster calculations. In addition to the basic adder design, we also propose a rectification logic which would enable higher accuracy for larger computations. Experimental results show that our adder produces results 91.2% faster than the conventional ripple-carry adder. In terms of accuracy, the addition of rectification logic to the basic design produces results that are more accurate than state-of-the-art adders like SARA and BCSA by 74%.
The project is guided by:
Hemanta Kumar Mondal, National Institute of Technology Durgapur
Shirshendu Das, Indian Institute of Technology Ropar
Dip Sankar Banerjee, Indian Institute of Technology Jodhpur
Power efficiency is one of the grand challenge problems facing computer architecture in recent years. Driven by the growth towards green computing, it is imperative to design architectures that can provide maximum power savings while incurring minimal overhead on real estate and performance. Towards this, we propose a state-preserving mechanism for dynamically configuring DRAM banks based on utilization. We propose a novel mechanism via which it is possible to dynamically power down and power on banks while taking the bank utilization and overall performance into account. Over extensive experimentation using memory-intensive applications, we can observe a power savings of up to 12.31% while incurring an average performance loss of 0.82% over baseline executions.
We designed a mess management software solution as a part of the CS351: Software Engineering undergraduate course. The project was also a part of the associated lab for the course. The entire design was implemented using django framework. The code was written in python. The project was carried out in a group of three students.
We designed a project management software solution as a part of the CS241: Database Management undergraduate course. The backend was implemented using DBMS software mySQL. The front end was written using php. Designing the web pages was done using HTML and CSS. The project was carried out in a group of three students.
As a part of CS360: Compilers Lab, we designed a basic compiler. The compiler was able to generate RISC-V assembly for a given C++ code with limited functionalities. The project was carried out in a group of three. The features of the compiler include syntax and semantic analysis and code generation. Necessary documentation was also compiled.