My research interest and experience lie in the domain of computer architecture, especially memory devices and hardware simulators. I am working as a graduate student researcher in the DArchR Research Group. My advisor is Prof. Jason Lowe-Power. I believe that it is an amazing time to work on memory sub-systems, mainly because these devices are slow, but also, these devices aren't as secure as we previously imagined. My current research is focused on understanding the implications of the memory security vulnerability called the rowhammer bug. I am also working under the guidance of Prof. Zubair Shafiq and Prof. Sam King in the same project. Other than that, I also work on extending and adding new features to the gem5 simulator. During my undergrad, I've worked on topics including security, energy efficiency and performance improvement of DRAM-based memories. Previously I've worked under the guidance of Dr. Dip Sankar Banerjee from Indian Institute of Technology Jodhpur, Dr. Shirshendu Das from Indian Institute of Technology Ropar, and Dr. Hemanta Kumar Mondal from National Institute of Technology Durgapur.

University of California Davis (2021 - Present)

Master of Science (MS) in Computer Science (GPA: 4.0/4.0)

Indian Institute of Information Technology Guwahati (2016 - 2020)

Bachelor of Technology (B. Tech.) in Computer Science and Engineering (CPI: 8.37/10)

• Best Paper Award (2nd Place) at 30th Great Lakes Symposium on Very Large Scale Integration (GLSVLSI) 2020.

• Best Poster Award in Student Research Symposium (SRS) held at HiPC 2019 among 33 other posters.

• Best Poster Award in Student Research Symposium (SRS) held at HiPC 2018 among 21 other posters.

• [Mar. 2021] Our paper titled 'Towards Enhanced System Efficiency While Mitigating Row Hammer' was accepted for publication in ACM Transactions on Architecture and Code Optimization.

• [Dec. 2020] Our papers titled 'Towards Row Sensitive DRAM Refresh through Retention Awareness' and 'ACLA: An Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction' were accepted in ISQED 2021.

• [May 2020] Completed Graduation

• [Mar. 2020] Our paper titled 'An Approximate Carry Estimating Simultaneous Adder with Rectification' was accepted at GLSVLSI 2020.

• [Dec. 2019] Our poster titled 'ACEP: An Accuracy-Configurable Carry Estimating Parallel Adder' was awarded the best poster award in SRS held at HiPC 2019.

• [Dec. 2018] Our poster titled 'State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency' was awarded the best poster award in SRS held at HiPC 2018.

• [Dec. 2018] Our paper titled 'State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency' was accepted in ISQED 2019.

• [Apr. 2017] Started to work in the domain of Computer Architecture.