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Wachirawit Ponghiran (Mint)
M.S. candidate, μComputing Lab., EE, KAIST
291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: wponghir at purdue.edu
Office: NanoSoC S-204
Educations
Mahidol Wittayanusorn School, Thailand (2009.3 - 2011.3)
KAIST, Department of Electrical Engineering B.S. (2011.8 - 2015.8)
KAIST, Department of Electrical Engineering M.S. (2015.8 - 2017.8)
Research Interests
Clock tree synthesis and optimization
Design for manufacturability (DFM)
Low-power design
Publications
Conference Papers
Daijoon Hyun, Wachirawit Ponghiran, and Youngsoo Shin, "Clock tree optimization through selective airgap insertion," Proc. Int'l Symp. on Quality Electronic Design (ISQED), Mar. 2017.
Wachirawit Ponghiran, Seongbo Shim, and Youngsoo Shin, "Cut mask optimization for multi-patterning directed self-assembly lithography," Proc. Design, Automation & Test in Europe (DATE), pp. 1498-1503, Mar. 2017.
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