PROFESSOR MEMBERS RESEARCH PUBLICATIONS NEWS ACTIVITIES CONTACTS
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Inhak Han (한인학)
Post Doctoral Researcher, μComputing Lab., EE, KAIST
291 Daehak-ro, Yuseong-gu, Daejeon 34141, Korea
Phone: +82-42-350-5479 / Fax: +82-42-351-9895
Email: drct1225 at kaist.ac.kr
Office: NanoSoC S-204
Personal Information
Date of Birth: June 10th, 1987
Place of Birth: Namwon, Korea
Hobbies: basketball
Educations
Seoul Science High School (2003.3 ~ 2005.2)
KAIST, Dept. of Electrical Engineering B.S. (2005.3 ~ 2010.2)
KAIST, Dept. of Electrical Engineering M.S. (2010.2 ~ 2012.2)
KAIST, Dept. of Electrical Engineering Ph.D. (2012.2 ~ 2017.6)
Miscellaneous Experiences
Internship @ IBM ARL (2011.07~2011.10)
Richard Newton Young Fellow Award at the 50th DAC (2013.06)
Internship @ LGE (2013.10~2014.04)
Internship @ Samsung Electronics (2015.07~2015.08)
Research Interests
Timing analysis
Thermal analysis
Logic synthesis
Pulsed latch circuits
Clock gating
Dual edge-triggered flip-flop
Publications
Journal Papers
I. Han and Y. Shin, "Folded circuit synthesis: min-area logic synthesis using dual-edge-triggered flip-flops," ACM ToDAES, vol. 23, no. 5, pp. 61:1-61:21, Aug. 2018.
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