Hyo-Jun Park
Semiconductor Device & Process Development Lab.
(Academic Advisor: Prof. Jun-Young Park)
[Head Student of Laboratory]
Address: Building E10, Room 204, Chungbuk National University
Contact: parkhjun@chungbuk.ac.kr
Semiconductor Device & Process Development Lab.
(Academic Advisor: Prof. Jun-Young Park)
[Head Student of Laboratory]
Address: Building E10, Room 204, Chungbuk National University
Contact: parkhjun@chungbuk.ac.kr
Chungbuk National University, Cheongju-si, Republic of Korea. Sep. 2023 – Present
Ph.D program in Semiconductor Engineering (Overall GPA: 4.40/4.50)
(Academic Advisor : Prof. Jun-Young Park)
Korea University, Sejong-Si, Republic of Korea. Mar. 2015 – Feb. 2022
Bachelor's degree in Electronics and Information Engineering (Overall GPA : 3.52/4.50)
→ Developing process technologies for enhancing device performance and reliability.
(Developed technologies: Low-Temperature Deuterium Annealing , Rapid Deuterium Annealing)
(Developing technology: Plasma Enhanced Deuterium Annealing)
→ Conducting stress tests on device to evaluate reliability and life-time.
(i.e. Electrical stress conditions, γ-ray radiation, microwave)
→ Mitigating the roughness of silicon (Si) and silicon dioxide (SiO2) layers caused by fabrication.
(i.e. Chemical Mechanical Polishing, Oxidation)
→ Fabricating MOSFETs based on enclosed-layout transistor (ELT) structure
→ Fabricating device: Silicon based MOSFETs (Dielectric - SiO2, HfO2)
→ Fabricated devices are used for analyzing effect of developing process technology
→ Simulations are conducted with Synopsys Sentaurus and Silvaco Atlas
→ Simulation agenda: Gate-All-Around Structure, Nanosheet FETs
→ Device Fabrication Processing
[6] Reactive Ion Etching, VITA 8 / Produced by Femto Science
[5] Mask Aligner, MA-6 / Produced by Karl Suss
[4] Rapid Thermal Annealing, RTP-100 / Produced by ULTECH
[3] Thermal Evaporator, KVE-EG / Produced by Korea Vaccum Tech
[2] Plasma Enhanced Deuterium Annealing / Custom-Made
[1] Thermal Deuterium Annealing (including LTDA & RDA) / Custom-Made
→ Device Characterization
[5] Surface Profiler, Alpha Step / Produced by KLA Tencor
[4] Optical Microscope, Eclipse LV150NA / Produced by Nikon
[3] Device Parameter Analyzer, Keithley 4200A-SCS / Produced by Keithley
[2] Device Parameter Analyzer, B1500A / Produced by Keysight
[1] Probe Station, MS-8000 / Produced by MS Tech
→ TCAD Simulation
[2] Sentaurus / Produced by Synopsys
[1] Atlas, Athena / Produced by Silvaco
→ Others
[2] Excel (VBA Function) / Produced by Microsoft
[1] Origin 2024 / Produced by Origin Lab
[13] M.-K. Lee, D.-E. Bang, S.-J. Chang, H.-J. Park, E.-C. Yun, S.-M. Kang, M.-W. Kim, D. Sohn, and J.-Y. Park, "Rapid Hydrogen Annealing for Enhanced Device Performance and Reduced Thermal Budget", Semicond. Sci. Technol., in press. [Website]
[12] D. Sohn, M.-K. Lee, J.-W. Yeon, M.-W. Kim, T.-H. Kil, E.-C. Yun, H.-J. Park, and J.-Y. Park, "V-Notch Shaped Contact Design in Nanosheet FETs for Enhancing Chip Performance", IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., in press. [Website]
[11] D. Sohn, M.-K. Lee, D.-E. Bang, H.-J. Park, E.-C. Yun, S.-M. Kang, M.-W. Kim, H. Jeon, and J.-Y. Park, "Wrap-Around Word-Line DRAM Cell Transistor Enabling Enhanced Read/Write Speed", IEEE Trans. Electron Devices, 73, no. 1, pp. 271-278, Jan. 2026. [Website]
[10] (Co-1st author) E.-C. Yun, H.-J. Park, M.-K. Lee, T.-H. Kil, J.-W. Yeon, M.-W. Kim, D. Sohn, and J.-Y. Park, "Demonstration of Rapid Deuterium Annealing for High-Performance MOSFETs with Reduced Thermal Budget", IEEE Trans. Electron Devices, vol. 73, no. 1, pp. 707-711, Jan. 2026. [Website]
[9] D.-E. Bang, M.-K. Lee, E.-C. Yun, T.-H. Kil, H.-J. Park, J.-W. Yeon, M.-W. Kim, S.-J. Jeon, A-Y. Kim, and J.-Y. Park, "Junction Depth Optimization in Trench Gate Nanosheet FETs for Reduced Off-State Current", Silicon, vol. 17, pp. 3565-3572, Nov. 2025. [Website]
[8] (Co-1st author) H.-J. Park, M.-K. Lee, E.-C. Yun, D. Sohn, M.-W. Kim, S.-M. Kang, H. Jeon, and J.-Y. Park, "Investigation of Inner Spacer-Less Nanosheet FETs from an Off-State Current Perspective", IEEE Access, vol. 13, pp. 199876-199882, Nov. 2025. [Website]
[7] M.-W. Kim, H.-J. Park, M.-K. Lee, E.-C. Yun, S.-M. Kang, D.-E. Bang, T.-H. Kil, D. Sohn, and J.-Y. Park, "Study on the Impact of Deuterium Annealing Duration on MOSFET Performance", Semicond. Sci. Technol., vol. 40, no. 11, pp. 1-6, Nov. 2025. [Website]
[6] (Co-1st author) S.-J. Jeon, H.-J. Park, S.-J. Chang, M.-K. Lee, E.-C. Yun, T.-H. Kil, J.-W. Yeon, M.-W. Kim, and J.-Y. Park, "First Demonstration of Rapid Deuterium Annealing for Interface Trap Reduction in HKMG MOSFETs", Semicond. Sci. Technol., vol. 40, no. 8, pp. 1-5, Aug. 2025. [Website]
[5] M.-K. Lee, H.-J. Park, T.-H. Kil, J.-W. Yeon, E.-C. Yun, M.-W. Kim, and J.-Y. Park, "W-Shaped Silicon Channels to Increase the Channel Perimeter and Improve the Output Current of Multi-Bridge-Channel FETs", Silicon, vol.17, pp. 817-823, Feb. 2025. [Website]
[4] J.-W. Yeon, H.-J. Park, E.-C. Yun, M.-K. Lee, T.-H. Kil, Y.-S. Kim, and J.-Y. Park, "Improvement of Surface Roughness in SiO2 Thin Films via Deuterium Annealing at 300 °C", IEEE Trans. Nanotechnol., vol. 24, pp. 54-58, Jan. 2025. [Website]
[3] J.-W. Yeon, S.-S. Yoon, H.-J. Park, T.-H. Kil, D.-H. Wang, K.-S. Lee, D.-H. Jung, J.-Y. Ku, and J.-Y. Park, "Investigation of Deuterium De-Passivation by Repetitive Thermal Stress in CMOS Fabrication", IEEE Trans. Device Mater. Reliab., vol. 24, no. 4, pp. 618-623, Dec. 2024. [Website]
[2] T.-H. Kil, J.-W. Yeon, H.-J. Park, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-M. Kang, and J.-Y. Park, "Low-Temperature Deuterium Annealing for HfO2/SiO2 Gate Dielectric in Silicon MOSFETs", IEEE J. Electron Devices Soc., vol. 12, no. 1, pp. 1030-1033, Dec. 2024. [Website]
[1] T.-H. Kil, H.-J. Park, J.-W. Yeon, M.-K. Lee, E.-C. Yun, and J.-Y. Park, "Durability of Low-Temperature Deuterium Annealing Against Ionizing Radiation in MOSFETs", IEEE Trans. Electron Devices, vol. 71, no. 9, pp. 5177-5181, Sep. 2024. [Website]
[5] A-Y. Kim, D.-E. Bang, H.-J. Park, T.-H. Kil, J.-W. Yeon, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, M.-S. Kim, and J.-Y. Park, "Study on Hetero Gate Dielectrics to Reduce Ambipolar Current in Nanosheet Tunneling FETs", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 38, no. 3, pp. 296-301, May 2025. [Website]
[4] S.-M. Kang, Y.-J. Choi, H.-J. Park, T.-H. Kil, J.-W. Yeon, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, M.-S. Kim, and J.-Y. Park, "Study on Multiple Post-Metallization Annealing for Enhancing the Performance and Reliability of Silicon MOSFETs", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 38, no. 2, pp. 187-192, Mar. 2025. [Website]
[3] H.-S. Jee, D. Sohn, J.-W. Yeon, T.-H. Kil, H.-J. Park, E.-C. Yun, M.-K. Lee, and J.-Y. Park, "Fabrication of Low-Cost Physically Unclonable Function (PUF) Chip using Multiple Process Variables", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 37, no. 5, pp. 527-532, Sep. 2024. [Website]
[2] (1st author) H.-J. Park, T.-H. Kil, J.-W. Yeon, M.-K. Lee, E.-C. Yun, and J.-Y. Park, "Recovery of Radiation-Induced Damage in MOSFETs using Low-Temperature Heat Treatment", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 37, no. 5, pp. 507-511, Sep. 2024. [Website]
[1] Y.-S. Kim, D.-H. Jung, H.-J. Park, J.-W. Yeon, T.-H. Kil, and J.-Y. Park, "Enhancement of SiO2 Uniformity by High-Pressure Deuterium Annealing", J. Korean Inst. Electr. Electron. Mater. Eng., vol. 37, no. 2, pp. 148-153, Mar. 2024. [Website]
[19] D. Sohn, S.-M. Kang, D.-E. Bang, E.-C. Yun, M.-K. Lee, H.-J. Park, M.-W. Kim, and J.-Y. Park, "DRAM Cell Transistor with Wrap-Around Word-Line (WAW) Structure for Enhancing Read/Write Performance", The 33rd Korean Conference on Semiconductors, Jan. 2026. – Poster Session
[18] S.-M. Kang, D.-E. Bang, D. Sohn, H.-J. Park, E.-C. Yun, M.-W. Kim, M.-S. Kim, and J.-Y. Park, "Multi-Level Cell Physically Unclonable Function (PUF) Based on Dual Physical Parameters in Silicon MOSFETs", The 33rd Korean Conference on Semiconductors, Jan. 2026. – Oral Session
[17] M.-W. Kim, H.-J. Park, E.-C. Yun, S.-M. Kang, D.-E. Bang, D. Sohn, and J.-Y. Park, "Comparative Study of Multiple High-Pressure Rapid Deuterium Annealing for MOSFET Performance Enhancement", The 33rd Korean Conference on Semiconductors, Jan. 2026. – Oral Session
[16] M.-W. Kim, H.-J. Park, E.-C. Yun, S.-M. Kang, D.-E. Bang, D. Sohn, and J.-Y. Park, "Study on the Efficiency of Deuterium Annealing for Various Process Durations", The 33rd Korean Conference on Semiconductors, Jan. 2026. – Poster Session
[15] Y.-S. Lee, E.-C. Yun, H.-J. Park, and J.-Y. Park, "Nanosheet FETs with an Inner Spacer Barrier for Suppression of Substrate Parasitic Effects and Punch-Through", The 33rd Korean Conference on Semiconductors, Jan. 2026. – Poster Session
[14] J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, D.-E. Bang, and J.-Y. Park, "Low-Temperature Deuterium Annealing for Improved Immunity against Hot-Carrier Injection in HKMG MOSFETs", The 32nd Korean Conference on Semiconductors, Feb. 2025. – Oral Session
[13] M.-K. Lee, H.-J. Park, E.-C. Yun, J.-W. Yeon, T.-H. Kil, M.-W. Kim, S.-J. Jeon, D.-E. Bang, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park, "Partial Trench Gate Nanosheet FETs for Enhanced ION/ IOFF Ratio", The 32nd Korean Conference on Semiconductors, Feb. 2025. – Poster Session
[12] D.-E. Bang, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park, "Junction Depth Engineered Trench Gate Nanosheet FETs for Suppressing Leakage Current in Parasitic Substrate Channels", The 32nd Korean Conference on Semiconductors, Feb. 2025 – Poster Session
[11] A-Y. Kim, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, D.-E. Bang, S.-M. Kang, and J.-Y. Park, "Hetero-Gate Dielectric Structures for Reducing Ambipolar Current in Nanosheet Tunneling FETs", The 32nd Korean Conference on Semiconductors, Feb. 2025. – Poster Session
[10] T.-H. Kil, J.-W. Yeon, H.-J. Park, D.-E. Bang, M.-K. Lee, E.-C. Yun, M.-W. Kim, S.-J. Jeon, D. Sohn, A-Y. Kim, S.-M. Kang, and J.-Y. Park, "Material Engineering of Inner Spacer in Nanosheet FETs to Reduce Off-State Current", The 32nd Korean Conference on Semiconductors, Feb. 2025. – Poster Session
[9] E.-C. Yun, J.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, H.-S. Jee, D. Sohn, S.-M. Kang, A.-Y. Kim, Y.-J. Choi, D.-E. Bang, and J.-Y. Park, "Spacer-Less Trench Gate Nanosheet FET for Improved On-State Current and Simplified Fabrication Process", KIEEME Annual Summer Conference 2024, Jun. 2024. – Poster Session
[8] T.-H. Kil, H.-J. Park, J.-W. Yeon, E.-C. Yun, M.-K. Lee, D. Sohn, H.-S. Jee, S.-M. Kang, A.-Y. Kim, Y.-J. Choi, D.-E. Bang, and J.-Y. Park, "Low-Temperature Deuterium Annealing for Enhanced Ionizing Radiation and Electrical Stress Immunity in MOSFETs", KIEEME Annual Summer Conference 2024, Jun. 2024 – Poster Session
[7] H.-S. Jee, D. Sohn, J.-W. Yeon, H.-J. Park, T.-H. Kil, E.-C. Yun, M.-K. Lee, S.-M. Kang, A.-Y. Kim, Y.-J. Choi, D.-E. Bang, and J.-Y. Park, "Development of Physically Unclonable Function (PUF) using Multiple Process Variables", KIEEME Annual Summer Conference 2024, Jun. 2024. – Poster Session
[6] Y.-J. Choi, S.-M. Kang, H.-J. Park, T.-H. Kil, J.-W. Yeon, H.-S. Jee, E.-C. Yun, M.-K. Lee, D. Sohn, D.-E. Bang, A.-Y. Kim, and J.-Y. Park, "Impact of Hydrogen Passivation after Deuterium Annealing in the Fabrication of Silicon MOSFETs", KIEEME Annual Summer Conference 2024, Jun. 2024. – Poster Session
[5] D.-E. Bang, A.-Y. Kim, Y.-W. Yeon, H.-J. Park, T.-H. Kil, M.-K. Lee, E.-C. Yun, D. Sohn, H.-S. Jee, S.-M. Kang, Y.-J. Choi, and J.-Y. Park, "Optimization of Doping Profile for Improved Performance of Nanosheet FET", KIEEME Annual Summer Conference 2024, Jun. 2024. – Poster Session
[4] J.-Y. Kim, S.-J. Lee, J.-W. Yeon, H.-J. Park, and J.-Y. Park, "Optimization of Doping Concentration for Improved Threshold Voltage Sensitivity of Junctionless FETs Fabricated on Silicon-on-Insulator Substrate", KIEEME Annual Summer Conference 2024, Jun. 2024. – Poster Session
[3] H.-J. Park, T.-H. Kil, J.-W. Yeon, and J.-Y. Park, "Study on the Sustainability of Low-Temperature Deuterium Annealing for Damaged Gate Dielectric by Ionizing Radiation", The 31th Korean Conference on Semiconductors, Jan. 2024. – Poster Session
[2] T.-H. Kil, J.-W. Yeon, H.-J. Park, and J.-Y. Park, "Impact of Low-temperature Deuterium Annealing for Poly-Si Channel Thin-Film Transistors", The 31th Korean Conference on Semiconductors, Jan. 2024. – Oral Session
[1] J.-W. Yeon, T.-H. Kil, H.-J. Park, and J.-Y. Park, "Improved MOSFETs Performance and Reliability by Low-temperature Deuterium Annealing", The 31th Korean Conference on Semiconductors, Jan. 2024. – Oral Session
[5] J.-Y. Park, D. Sohn, H.-J. Park, E.-C. Yun, 측면 채널을 둘러싸는 매립형 워드 라인 구조를 갖는 DRAM 셀 트랜지스터 및 그 제조 방법, KR 10-2026-0006170, 2026.01.13.
[4] J.-Y. Park, D. Sohn, M.-W. Kim, J.-W. Yeon, H.-J. Park, M.-K. Lee, E.-C. Yun, 브이-노치 메탈 접촉 구조를 갖는 나노시트 반도체소자 및 그의 제조방법, KR 10-2025-0080331, 2025.06.18.
[3] J.-Y. Park, M.-K. Lee, T.-H. Kil, H.-J. Park, E.-C. Yun, J.-W. Yeon, H.-S. Jee, 커브드 채널을 갖는 나노시트 반도체소자 제조방법 및 이에 의하여 제조된 나노시트 반도체소자, KR 10-2024-0096067, 2024.07.22.
[2] J.-Y. Park, J.-W. Yeon, T.-H. Kil, H.-J. Park, Y.-J. Choi, S.-M. Kang, H.-S. Jee, 박막의 표면 거칠기 및 균일성 개선을 위한 저온 중수소 어닐링 방법 및 이에 의하여 제조된 반도체 소자, KR 10-2024-0053442, 2024.04.22.
[1] J.-Y. Park, J.-W. Yeon, H.-J. Park, T.-H. Kil, 급속 중수소 열처리 시스템 및 이를 이용한 열처리 방법, KR 10-2024-0029983, 2024.02.29
[1] Chungbuk National University President's Award
2024 Chungbuk PRIDE Standard Field training Matching Day by Chungbuk National University
[1] Internship Program Dec. 2021 – Feb. 2022
→ PSK Inc. (Manufacturing Ultrasonic Asher and Plasma Etcher)
→ Assisting process engineer by tuning or assessing process recipe to stabilize PRECIA (Plasma Bevel Etcher)