Junga Lee

Motivated and experienced VLSI design engineer with 7+ years of experience in system development, VLSI design and verification for SoC projects including mobile and wearable devices. Experienced from GPU IP level verification to Full-chip level integration and verification including development environment management. Performed 10+ commercialization projects ranging from chip design to silicon experience. Also have handling various tools experience including NC Verilog, spyglass and so on with script language.

Feb 2025 - Present KAIST, Republic of Korea

• M.S. in Electrical Engineering 

• Adivsor: Prof. Minsoo Rhu

Mar 2013 - Feb 2017 Hanyang university, Republic of Korea

• B.S. in Economics & Finances and Computer Science & Engineering as Double Major

• CUM LAUDE

Mar 2024 - Present Staff Engineer , Samsung Electronics, Republic of Korea

Aug 2017 - Feb 2024 Engineer , Samsung Electronics, Republic of Korea

• SoC H/W design (Nov 2019  - Present)

  • Experienced 10+ SoC projects including mobile and wearable devices

  • IP/Block/Full-chip level design and integration

  • Block/Full-chip level verification for RTL and Gate-level

  • PAD/Package design

• SGPU IP verification (Aug 2017 - Nov 2019)

  • Function and Formal verification

VLSI SoC deseign and architecture, hardware accelerator design