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Job Roles
Assistant Professor, Silicon University, Bhubaneswar, India (Sept.2024-till date)
Ph.D. Research Scholar, VLSI Research Group, NIT Rourkela (2018-2024)
(https://sites.google.com/view/profkkm/people_1)Project Research Assistant, SMDP C2S@MeitY (10 months)
Lecturer, School of Elecronics Engineering, KIIT Deemed to be University (on Study Leave) 2015-2022
Projects:
1) Co-PI for SMDP C2S Tool Support Program, MeitY, Govt. of India
Positions/Responsibility:
1) Faculty (additional appointment) at Advanced VLSI Lab, Silicon University
CONTACT DETAILS:
Email: joychowdhury87@yahoo.in
Publication Details: https://www.researchgate.net/profile/Joy-Chowdhury-4/publications
Google Scholar : https://scholar.google.com/citations?hl=en&user=2vA9RG8AAAAJ&view_op=list_works&gmla=AOAOcb01qzm3im3Wc4rgiq-lrEAXLEXfpDC1pkcTg3BfMQCODadvuIMbX4bgfbwBUKmWS5JQteF1wJ0gDtMbeUS8
Research Interests
Research Interests
VLSI Design and Embedded Systems
Nano-electronic device modeling and simulation
Emerging Nano-Transistors, Memristors, Quantum devices
Bio-sensors, biomedical device development
Smart city and Smart electronics
Hardware security
Digital system Design and Verification
ASIC Design, RTL-GDSII
Training and Skill Development
Training and Skill Development
RTL to GDSII using Open Source Tools (Icarus Verilog, Yosys, OpenRoad, etc.)
RTL to GDSII using Cadence Tool Suite and Synopsys Tool Chain
Digital System Design and Verification Using FPGA
Digital System Verification using System Verilog
RISC-V implementation in Verilog and FPGA
(https://github.com/silicon-vlsi/SI-2025-DigitalVLSI)Industry Specific Academic Training in the Domain of Digital VLSI Design, Verification, Design for Testability, Design for Manufacturability, Testing.
ASIC SoC Design
Subject Taught/Interest
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