Advanced 2.5/3D packaging boosts the inter-die data transportation bandwidth, which is ultimately important to high-performance computing. However, testing the high-speed, high-density interconnects poses serious challenges to manufacturing testing.

We address this issue by developing design-for-test circuitry that facilitates inter-die interconnect testing. As the number of interconnects keeps growing, repair becomes mandatory to ensure profitable yield. Thus, we further develop interconnect repair methodologies with physical and timing constraints considered.

With their widespread penetration into our lives, embedded systems must be protected from malicious access.

In this area, we are interested in the following topics.

• Design-for-security: Design methodologies for HW components, e.g., microcontrollers, memory, and cryptography accelerators, to improve the protection over side-channel-attack (SCA) and fault-injection-attack (FIA).

• Security hardware: Design of hardware components or systems to facilitate security policies, e.g., security co-processor.

For mission-critical applications, e.g., avionics and automotive electronics, software-based self-test is a promising solution to complement the mainstream scan-based manufacturing/online testing. SBST has the following advantages:

• Inherently online and functional.

• No extra design-for-test (DfT) circuitry.

• Flexible test scheduling.

SBST test program generation is essentially a sequential test generation problem. The goal of our SBST research is to provide a fully automated SBST solution.

The quest for a more powerful ATPG is ever-lasting.

To address this issue, our main interest is parallel ATPG with attention to preserving determinism. In addition, we also investigate to improve basic ATPG components, including testability analysis and learning.