Analog Mixed Signal Design Experience:

HBM3, SerDes, PLL, PMIC, Sensor Interface, ADC, Wireline Transceivers

(Intel & Terminus Circuits) – Relevant Publications 

1.     High Bandwidth Memory (HBM)

a.     HBM3 PHY IP design at 7.2Gbps with 0.5pJ/bit

 i.      Published in VLSID 2025

b.     TX / RX Design – Supervision and Design – HBM3 (6.4 Gbps),

c.     High Speed View – TX + RX (6.4Gbps) with ESD compliance to HBM / CDM.

d.      Duty Cycle Correction (DCC in Strobe Path – Unmatched RX Arch)

                                               i. Published in IEEE SOCC 2022

e.     Capacitorless LDO for 230mA high current load

                                               i. Published in VLSID 2022

       2.     Power Management IC design (PMIC)

a. Capacitorless LDO for 230mA high current load

                                               i. Published in VLSID 2022

b. Dual mode power supply1.2V/1.8V LDO 4-24mA current load

i. Published in VDAT 2024

3.  SerDes / Serial IO / High Speed Serial Links    

SerDes TX Design – 1.25 Gbps to 20Gbps

a.      Mentored the publication in IEEE CONECCT 2020

b.     Dual Mux Latch based High Speed Serializer (Masters Thesis – Intern #2)

4.     SerDes RX Design – Front End AFE (CTLE + DFE) – 1.25Gbps to 20Gbps [PCIe Gen4/USB 3.2]

a.      Inductorless CTLE with tunable zero-pole for 20Gbps RX

                                               i. Published in Microelectronics Journal, 2020

b.     Active Inductor Front End design with CTLE and tunable centre frequency for 10G – 20Gbps

                                               i. Published in AEUE Journal, 2019

                                             ii. Simulations work are published in IEEE CONECCT 2019

1.     Mentored a Masters Thesis – Intern #1

5.     SerDes RX Design – Front End AFE (Low Freq and High Freq path) [MIPI MPHY – 11.36Gbps]

a.      UFS 2.0 Protocol support for MIPI MPHY HS-Gear 4/PWM-G7

6.     High Frequency PLL Design –

1. LC VCO for 8GHz/16GHz PLL with SSC [PCIe Gen4/3]

2. LC VCO for 10GHz PLL for USB 3.2 / Multi Standard SerDes 10Gbps / Wireline Transceivers

a.      Frequency Doubler for 20GHz selection

b.     Published in IEEE IMaRC 2018, IMaRC 2019, VDAT 2019

3. Ring VCO for 2.5G/5.0G [PCIe Gen1/2, USB 3.1/3.2]

a.     Published in IEEE VLSID 2021, Electronics Letters 2019

7. Post Silicon Characterization     

Test Plan Generation for Post Silicon Characterization focusing on Analog Characterization – Bench Test / High Volume Test.

a.      HBM3

b.     PCIe Gen4

c.      USB 3.2

d.     MIPI MPHY HS Gear 4

8.     Capacitor Sensor Interface Design

a.      IDC Sensor Design for Lab-on-Chip

                                               i. Published in VLSID 2017

b.     High Gain Signal Conditioning and Read Out

c.      Noise Analysis of Ring Oscillator based sensor interface

                                               i. Published in ISCAS 2016, MWS CAS 2016

9. Sigma Delta ADC design

                                               i. Published in IEEE SOCC 2017