Course DescriptionÂ
Review of computer design principles, processor design, RISC processors, pipelining, and memory hierarchy. Instruction level parallelism (ILP), dynamic scheduling, multiple issue, speculative execution, and branch prediction. Limits on ILP and software approaches to exploit more ILP. VLIW and EPIC approaches. Thread-level parallelism, multiprocessors, chip multiprocessors, and multi-threading. Cache coherence and memory consistency. Advanced memory hierarchy design, cache and memory optimizations, and memory technologies. Advanced topics in storage systems. Designing and evaluating I/O systems. (3 Credit Hours)
Announcements
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Grades and assignments are posted on the Teams platform.
Slides
00 Course IntroductionÂ
05 Instruction-Level Parallelism and it Exploitation (Part 1)
06 Instruction-Level Parallelism and it Exploitation (Part 2)
07 Instruction-Level Parallelism and it Exploitation (Part 3)
12 Warehouse Scale Computers
13 Domain-Specific Architectures