Intelligent Integrated Circuits and Systems Lab

Our research focuses on the development and verification of energy-efficient, high-performance mixed-signal integrated circuit (IC) architectures in CMOS technologies. In particular, our research interest includes the following areas: 1) Artificial intelligence (AI)-integrated circuits for applications in edge robotics and the Tactile Internet, 2) In-memory, near-memory, and processing-in-memory architectures using the next-generation memory, 3) Low-latency transceiver IC for applications in the Tactile Internet, 4) High-speed parallel transceiver supporting various Ethernet standards.

Any research topic not listed above can be considered as our future research area. Please feel free to contact us!

We are looking for self-motivated students.
Please send your CV and transcript to jonghyeok.yoon at dgist.ac.kr if you are interested.

지능형 집적 회로 및 시스템 연구실에서 함께 연구하실 석사, 박사 과정 학생들을 모집합니다.
CV와 성적표를 첨부하여 jonghyeok.yoon at dgist.ac.kr로 메일 주세요.

Research

Edge-intelligent IC

Processing-in-memory architectures

Image: UPMEM

Multi-standard
high-speed transceiver

Recent works

A 8.79 TOPS/W neuromorphic simultaneous localization and mapping (NeuroSLAM) accelerator for edge devices

IEEE ISSCC, Feb. 2020 &
IEEE JSSC, Jan. 2021.
[Article:https://lnkd.in/dZ4xzEv]

Jong-Hyeok Yoon et al.

A 56.67 TOPS/W compute-in-memory/digital RRAM macro with active-feedback-based read and in-situ write verification

IEEE ISSCC, Feb. 2021 &
IEEE JSSC, Jan. 2022.
[Article:https://bit.ly/30RwYbS]

Jong-Hyeok Yoon et al.

A 118.44TOPS/W ternary-weight compute-in-memory RRAM macro with voltage-sensing read and write Verification for reliable multi-bit RRAM operation

IEEE CICC, Apr. 2021. &
IEEE JSSC, Mar. 2022.
[The Best Regular Paper Award]
[Article:https://b.gatech.edu/343qE2E]

Jong-Hyeok Yoon et al.

A 3.125-to-28.125 Gb/s multi-standard transceiver with a fully channel-independent operation

IEEE CICC, Apr. 2018 &
IEEE TCAS-I, Aug. 2020.

Jong-Hyeok Yoon et al.

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Intelligent Integrated Circuits and Systems Lab

Edge-intelligent IC

Processing-in-memory architectures

Multi-standard high-speed transceiver

A 8.79 TOPS/W neuromorphic simultaneous localization and mapping (NeuroSLAM) accelerator for edge devices

A 56.67 TOPS/W compute-in-memory/digital RRAM macro with active-feedback-based read and in-situ write verification

A 118.44TOPS/W ternary-weight compute-in-memory RRAM macro with voltage-sensing read and write Verification for reliable multi-bit RRAM operation

A 3.125-to-28.125 Gb/s multi-standard transceiver with a fully channel-independent operation

Multi-standard
high-speed transceiver