Publications

< Journal >

• Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Songi Cheon, Hyunsu Jang, Junyoung Song*, "A 1.58 pJ/b 9 G bps Reference-Less Clock and Data Recovery Circuit With Sigma Range Detector," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 7, pp. 888-892, July 2025. (IF=4.9)

• Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Bongsu Kim, Hyunsu Jang, Sewook Hwang, Junyoung Song*, "A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit," in IEEE Transactions on VLSI Systems, vol. 32, no. 6, pp. 1169-1172, Jun. 2024. (IF=2.8)

• Hyunsu Park, Seung-Myeong Yu, Junyoung Song*, "An 11 Gb/s 0.376 pJ/Bit Capacitor-Less Dicode Transceiver With Pattern-Dependent Equalizations TIA Termination for Parallel DRAM Interfaces," in IEEE ACCESS, vol. 12, pp. 145934-145943, 2024. (IF=3.9)

• Bongsu Kim, Seung-Myeong Yu, Jongchan An, Gwangmyeong An, Junyoung Song*, "A High Power Supply Rejection and Fast-transient LDO with Feed-forward Compensation using Current Sensing Technique," in Journal of Semiconductor Technology and Science, Vol. 24, No. 1, pp. 41-46, Jun. 2024. (IF=0.5)

• Mokurala Krishnaiah, Teja M. Patil, Ajit Kumar, Junyoung Song*, Sung Hun Jin*, "Thermal stability on solid state symmetric supercapacitors with hydrothermally synthesized Cu2CoSnS4 electrodes," in Materials letters, vol. 352, no. 12, pp. 1-4, Dec. 2023. (IF=2.7)

•  Jongchan An, Seung-Myeong Yu, Junwon Jeong, Junyoung Song*, "A Digital FLL-based Sub-harmonically Injection-locked PLL with Resolution-multiplied TDC for Frequency Offset Cancellation," in Journal of Semiconductor Technology and Science, Vol. 23, No. 3, pp. 202-205, Jun. 2023. (IF=0.4)

•  Ju Eon Kim, Dong-Hyun Yoon, Junyoung Song, Kwang-Hyun Baek, Jung-Hwan Choi, Tony Tae-Hyoung Kim, "A 6 Gbps PAM-3 Transceiver with Time-Varying Offset Compensation,"  in IEEE Solid-State Circuits Letters, vol. 6, pp. 85-88, 2023. (IF=2.7)

• Minseob Shim, Junwon Jeong, Junyoung Song, Yongtae Kim, Woong Choi*, "Segmented Match-Line and Charge-Sharing Based Low-Cost TCAM," IEEE Transactions on Circuits and Systems II, vol. 69, no. 12, pp. 5104-5108, Dec. 2022. (IF=3.691)

• M. Krishnaiah, A. Kumar, AK Kushwaha, Junyoung Song*, SungHun Jin*, "Thickness dependent photodetection properties of solution-processed CuI films: Towards cost-effective flexible visible photodetectors," Materials letters, vol. 305, no. 12, pp. 1-4, Dec. 2021. (IF=3.423)

• Yunha Kang, Junyoung Song*, "A 0.88-pJ/bit 28 Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21 dB loss compensation in 65nm CMOS process," IEICE Electronics Express, vol. 18, no. 18, pp. 1-5, Sep. 2021. (IF=0.578)

• Junyoung Song, Sewook Hwang, Chulwoo Kim*, “"A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology,” IEEE Transactions on VLSI Systems, vol. 29, no. 8, pp. 1567-1574, Aug. 2021. (IF=2.312)

• Nahyun Kim, Junyoung Song, "High-PSRR Low-dropout Regulator with Fast Transient Response Time and Low Output Peak Voltage," Journal of Semiconductor Technology and Science, Vol. 21, No. 4, pp. 292-296, Aug. 2021. (IF=0.474)

• Purnendu Kartikay, M. Krishnaiah, B. Sharma, R. Kail, N. Mukurala, D. Mishra, A. Kumar, S. Mallick*, Junyoung Song, SungHun Jin*, "Recent advances and challenges in solar photovoltaic and energy storage materials: future directions in Indian perspective," Journal of physics-energy, vol. 3, no. 3, pp. 1-41, Jul. 2021. (IF=5.967)

• Jinheon Jeong, Seung Gi Seo, Seung-Myeng Yu, Yunha Kang, Junyoung Song*, SungHun Jin*, "Flexible Light-to-Frequency Conversion Circuits Built with Si-Based Frequency-to-Digital Converters via Complementary Photosensitive Ring Oscillators with p-Type SWNT and n-Type a-IGZO Thin Film Transistors," Small, vol. 17, no. 36, pp. 1-10, Jul. 2021. (IF=13.281)

• M. Krishnaiah, Yun Jae Jeong, Rajneesh Kumar Mishra, Myung Jong Kim, Junyoung Song*, SungHun Jin*, "Temperature-Time profile effects on evolution of physical and electronic properties in visible light Cu2CoSnS4 photodetectors," Materials science in semiconductor processing, vol. 121, no. 1, pp. 1-9, Jan. 2021. (IF=3.927)

• M. Krishnaiah, A. Kumar, Junyoung Song*, Sung Hun Jin*, "Cu/(Co plus Sn) ratio effects on physical and photodetective properties for visible light absorbing Cu2CoSnS4 nanoparticles via a one-pot hydrothermal process" Journal of alloys and compounds, vol. 847, no. 12, pp. 1-13, Dec. 2020. (IF=5.316)

• M. Krishnaiah, A. Kumar, Junyoung Song*, SungHun Jin*, "Physical and electrical properties of Cu2CoSnS4 nanoparticles synthesized by hydrothermal growth at different reaction time and copper concentration," Data in Brief, vol. 32, no. 10, pp. 1-19, Oct. 2020. (IF=1.13)

• Hyunsu Park, Junyoung Song, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Jeongsik Yoo, Chulwoo Kim*, "30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links," IEEE Journal of  Solid-State Circuits, vol. 56, no. 2, pp. 581-590, Jul. 2020. (IF=5.013)

• Junyoung Song, Yongtae Kim, Chulwoo Kim*, “A 9Gb/s/ch transceiver with reference-less data-embedded pseudo-differential clock signaling for graphics memory interfaces,” IEEE Transactions on Circuits and Systems II, vol. 66, no. 12, pp. 1982-1986, Feb. 2019. (IF=3.292)

• Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang-Geun Bae, Jaehun Jun, Chulwoo Kim*,  “12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces,” IEEE Journal of  Solid-State Circuits, vol. 52, no. 2, pp. 463-475, Feb. 2019. (IF=5.013)

• Sang-Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim*, “A ΔΣ-Modulator based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for PLL Loop Bandwidth,” IEEE Transactions on Circuits and Systems II, vol. 66, no. 2, pp. 192-196, Feb. 2019. (IF=3.292)

•  Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim*, “A 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascaded-equalizer for post-LPDDR4 interfaces,” IEEE Transactions on Circuits and Systems I, vol. 65, no. 1, pp. 331-342, Jan. 2018. (IF=3.605)

• Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim*, “A 1.62−5.4 Gb/s receiver for DisplayPort version 1.2a with adaptive equalization and referenceless frequency acquisition techniques,” IEEE Transactions on Circuits and Systems I, vol. 64, no. 10, pp. 2691-2702, Oct. 2017. (IF=3.605) (IF=3.605)

• Jungtaek You, Junyoung Song, and Chulwoo Kim* “A 2Gb/s/ch data-dependent swing-limited on-chip signaling for single-ended global I/O in SDRAM,” IEEE Transactions on Circuits and Systems II, vol. 64, no. 10, pp. 1207-1211, Oct. 2017. (IF=3.292)

• Baekseok Ko, Joowon Kim, Jaemin Ryoo, Chulsoon Hwang, Junyoung Song, Soo-Won Kim*, “Simplified chip power modeling methodology without netlist information in early stage of SoC design process,” IEEE Trans. Components, Packaging, and Manufacturing Technology, vol. 6, no. 10, pp. 1513-1521, Oct. 2016. (IF=1.738)

• Ja-Young Kim, Junyoung Song, Jungtaek You, Sewook Hwang, Sang-Geun bae, and Chulwoo Kim*, “A 250Mb/s to 6Gb/s reference-less clock and data recovery  circuit with clock frequency multiplier,” IEEE Transactions on Circuits and Systems II, vol. 64, no. 6, pp. 650-654, Jun. 2017.

• Junyoung Song, Hyun-Woo Lee, Sewook Hwang, and Chulwoo Kim*, "A 10Gb/s/pin DFE-less Graphics DRAM Interface with Adaptive-bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique," IEEE Transactions on VLSI Systems, vol. 25, no. 1, pp 344-353, Jan. 2017.

• Junyoung Song, Sewook Hwang and Chulwoo Kim*, "A 4×5Gb/s 1.12us locking time Reference-less Receiver with Asynchronous Sampling-based Frequency Acquisition and Clock Shared Sub-channels," IEEE Transactions on VLSI Systems, vol. 24, no. 8, pp 2768-2777, Aug. 2016.

• Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim*, “An addon type real-time jitter tolerance enhancer for digital communication receivers,” IEEE Transactions on VLSI Systems, vol. 24, no. 3, pp 1092-1103, Mar. 2016.

• Changsung Choi, Sewook Hwang, Junyoung Song, Chulwoo Kim*, “2.56GHz sub-harmonically injection-locked PLL with cascaded DLL for multi-phase injection,” IET Electronics Letters, vol. 50, no. 24, pp. 1803-1804, Dec. 2014.

• Junyoung Song, Sewook Hwang, Hyun-Woo Lee, and Chulwoo Kim*, “A 7.5Gb/s reference-less transceiver with adaptive equalization and bandwidth-shifting technique for ultra-high-definition television in 0.13μm CMOS process,” IEEE Transactions on Circuits and Systems II, vol. 61, no. 11, pp. 865-869, Nov. 2014.

• Junyoung Song, Sewook Hwang and Chulwoo Kim*, “A 6Gb/s transmitter with data-dependent jitter reduction technique for DisplayPort physical layer,” Analog Integrated Circuits and Signal Processing, vol. 81, no. 2, pp. 529-536, Nov. 2014.

• Sewook Hwang, Junyoung Song, Sang-Geun Bae, and Chulwoo Kim*, “A 3Gb/s transmitter with a tapless pre-emphasis CML output driver," Analog Integrated Circuits and Signal Processing, vol. 81, no. 2, pp. 461-469, Nov. 2014.

• Kyeong-Min Kim, Sewook Hwang, Junyoung Song, and Chulwoo Kim*, “A 11.2Gbps LVDS receiver with a wide input range comparator,” IEEE Transactions on VLSI Systems, vol. 22, no. 10, pp. 2156-2163, Oct. 2014.

• Junyoung Song, Sewook Hwang, Tae-Chan Kim, Chulwoo Kim*, “A 400MHz-1.5GHz all digital integer-N PLL with a reference spur reduction technique,” Analog Integrated Circuits and Signal Processing, vol. 79, no. 1, pp. 183-189, Apr. 2014.

• Soo-Bin Lim, Hyun-Woo Lee, Junyoung Song, and Chulwoo Kim*, "A 247uW 800Mb/s/pin DLL-based data self-Aligner for through silicon via (TSV) interface," IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 711-723, Mar. 2013.

• Junyoung Song, Inhwa Jung, Minyoung Song, YongTae Kim, Young-Ho Kwak, Woonhyung Heo, Phi-Hung Pham, Sewook Hwang, and Chulwoo Kim*, “A 2.7Gb/s referenceless transceiver for DisplayPort v1.1a with weighted phase and frequency detection technique for random signal,” IEEE Transactions on Circuits and Systems I, vol. 60, no. 2, pp. 268-278, Feb. 2013.

• Phi-Hung Pham, Junyoung Song, Jongsun Park, and Chulwoo Kim*, “Design and implementation of an on-chip permutation network for multiprocessor system-on-chip,” IEEE Transactions on  VLSI Systems, vol. 21, no. 1, pp. 173-177, Jan. 2013.

• Junyoung Song, Inhwa Jung, Sewook Hwang, and Chulwoo Kim*, "A self-impedance calibrated PVT-insensitive pseudo open drain (POD) output driver without external resistors," IET Electronics Letters, vol. 48, no. 22, pp. 1394-1395, Oct. 2012.

< International Conference >

• Ju Eon Kim, Dong-Hyun Yoon, Junyoung Song, Kwang-Hyun Baek, Jung-Hwan Choi, Tony Tae-Hyoung Kim, "A 6 Gbps PAM-3 Transceiver with Time-Varying Offset Compensation," 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2022, pp. 1-3.

• Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim*, "A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces," in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022, pp. 452-453.

• Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chuwoo Kim*, "A 3bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver using One-Tap DFE for Next Generation Memory Interface," in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019, pp. 382-383.

•  Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim*, “12Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling with 100% Data Payload and Spread Transition Scheme for 8K UHD Intra-panel Interfaces,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2017, pp. 490-491.

• Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim*, "A 32Gb/s Rx Only Equalization Transceiver with 1-tap Speculative FIR and 2-tap Direct IIR DFE", in IEEE Symp. On VLSI Circuits (VLSIC), Jun. 2016, pp. 46-47. 

• Junyoung Song, Hyun-Woo Lee, Jayoung Kim, Sewook Hwang, and Chulwoo Kim*, "1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces," in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2015, pp. 1-3.

• Hyun-Woo Lee, Junyoung Song, Sang-Ah Hyun, Seunggeun Baek, Yuri Lim, Jungwan Lee, Minsu Park, Haerang Choi, Changkyu Choi, Jinyoup Cha, Jaeil Kim, Hoon Choi, Seungwook Kwack, Yonggu Kang, Jongsam Kim, Junghoon Park, Jonghwan Kim, Jinhee Cho, Chulwoo Kim, Yunsaing Kim, Jaejin Lee, Byongtae Chung, and Sungjoo Hong*, “A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2014, pp. 434-435.

• Junyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, and Chulwoo Kim*, “An adaptive bandwidth PLL for avoiding noise interference and DFE-less fast pre-charge sampling for over 10Gb/s/pin Graphics DRAM interface,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2013, pp. 312-313.

• Junyoung Song, Hyun-woo Lee, Sewook Hwang, Inhwa Jung, and Chulwoo Kim*, “ A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13μm CMOS process,” in IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2013, pp. 89-90.

• Sewook Hwang, Inhwa Jung, Junyoung Song, and Chulwoo Kim*, “A 5.4Gb/S adaptive equalizer with unit pulse charging technique in 0.13μm CMOS.” in IEEE International Symposium on Circuits & Systems (ISCAS), May. 2012, pp. 1959-1962.

• Hyun-Woo Lee, Soobin Lim, Junyoung Song, Ja-Beom Koo, Dae-Han Kwon, Jong-Ho Kang, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, and Chulwoo Kim*, "A 283.2uW 800Mb/s/pin DLL-based data self-aligner for through silicon via(TSV) Interface, " in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2012. Pp. 48-50.

• Jabeom Koo, Gil-su Kim, Junyoung Song, Kwan-Weon Kim, Young Jung Choi, and Chulwoo Kim*, "small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application," in IEEE Custom Integrated Circuits Conference (CICC), Sep. 2009, pp. 717-720.

< Magazine >

•  Chulwoo Kim, Hyun-Woo Lee, Junyoung Song, “Memory interfaces: past, present, and future,” IEEE Solid-State Circuits Magazine, vol. 8, no. 2, pp-23-34, Jun. 2016.

< Book >

•  Chulwoo Kim, Hyun-Woo Lee, Junyoung Song, “High-bandwidth memory interface,” Springer, Nov. 2013.