IC Gallery
60-GHz RF downconversion mixer for 5G applications
Blocks: Down-conversion mixer, LO buffer
Process: 65nm CMOS process
Designer: I. Nam and C. Choi
Work published in IEEE Microwave and Wireless Components Letters 2017
24-GHz RF transmitter for in-cabin radar systems
Blocks: Power amplifier, I/Q up-conversion mixer, I/Q LO generator
Process: 65nm CMOS process
Designer: S. Lee, Y. Jeon, G. Park, J. Myung, S. Lee, O. Lee, H. Moon and I. Nam
Work published in Electronics 2020
60-GHz RF downconversion mixer for 5G applications
Blocks: Down-conversion mixer, LO buffer
Process: 65nm CMOS process
Designer: I. Nam and C. Choi
Work published in IEEE Microwave and Wireless Components Letters 2017
MedRadio receiver front-end with inverter-based complementary switching mixer
Blocks: LNA, I/Q mixer, LO buffer, and polyphse filter
Process: 180nm CMOS process
Designer: I. Nam and C. Choi
Work published in IEEE Microwave and Wireless Components Letters 2016
World first multistandard multimode mobile digital TV tuner for DVB-H/T, T-DMB, and ISDB-T (which developed in Samsung Electronics, 2005)
Mass production
Process: 180nm CMOS process
Designer: I. Nam, et. al.
Work published in JSTS 2015
A wideband digital TV receiver front-end with noise and distortion cancellation
Blocks: LNA, mixer
Process: 130nm CMOS process
Designer: D. Im and I. Nam
Work published in TCAS-I 2014
Low-IF receiver and direct-conversion transmitter for ZigBee applications
Blocks: Receiver, Transmitter, LO chain, SPI
Process: TSMC 180nm CMOS process
Size: 1mm x 0.9mm
Designer: I. Nam, et. al
Work published in IEEE Trans. Micro. Theory and Tech. 2007
Down-conversion mixer & operational amplifier for direct-conversion receiver
Blocks: Down-conversion Mixer
Process: TSMC 180nm CMOS process
Designer: I. Nam
Work published in IEEE Journal of Solid-State Circuits 2005
Low power low-IF receiver and direct-conversion transmitter for IEEE 802.15.4 WPAN applications
World first transceiver prototype satisfying IEEE802.15.4
Blocks: Receiver, Transmtter, LO chain, SPI
Process: TSMC 180nm CMOS process
Size: 3.5mm x 2.5mm
Designer: P. Choi, H. C. Park, S. Kim, S. Park, I. Nam, et. al
Work published in IEEE JSSC & ISSCC 2003