Research
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High Bandwidth Memory Interface
High Bandwidth Memory Interface
Development of encoding scheme for data-dependent noise elimination
Our signaling method improves Xtalk on next-generation HBM with extreme channel density.
HBM requires a lot of power to provide the necessary bandwidth for processing large amounts of data. To address this, low-power technologies can be applied, such as reducing voltage or introducing dynamic power management techniques.
DRAM-PIM
DRAM-PIM
Developing optimized data transmission paths for high transmission speeds and low latency
Designing and implementing interface circuits to ensure stable signals and data integrity
Improving the performance and energy efficiency of DRAM PIM for AI and big data analysis
Performance Modeling for I/O Links
Performance Modeling for I/O Links
Modeling and design methodology for transceivers
Machine learning-based performance modeling
Design framework for automation and optimization
High-performance, Low-Power CDR
High-performance, Low-Power CDR
The noisy input data should be recovered to clean data and clock through CDR.
CDR with better performance requires a lot of power consumption.
We study how to design the high-performance CDR energy efficiently.
Artificial Intelligence Hardware Accelerator
Artificial Intelligence Hardware Accelerator
Designing power efficient and small area modules to accelerate the AI system on chip
Developing novel mixed domain neuron that advantages with analog domain properties
Analyzing the vulnerability of the neurons and calibrating with additional modules and architecture
Researching future neuromorphic architecture and device, spiking neural network and resistive RAM
Privacy-Preserving Deep Learning System Using Homomorphic Encryption
Privacy-Preserving Deep Learning System Using Homomorphic Encryption
Developing and evaluating end-to-end HE-based cryptographic protocols for privacy-preserving inference/training of various deep learning models
Implementing and optimizing hardware acceleration of the developed protocol on existing computing platforms (GPU and FPGA) and evaluate the performance
Creating ASICs with novel architecture and custom datapath implementation that can outperform CPUs, then evaluating their power/performance/area
Neural Network based Equalizer for Wireline Communication
Neural Network based Equalizer for Wireline Communication
Wireline communication serves as the backbone of the communication network. With the growing demand for high-bandwidth applications like video streaming and cloud services, the data transfer rates required for wireline communication keeps increasing, making the channel loss a major obstacle in achieving low bit error rate (BER). Equalization techniques such as FFE and DFE are commonly used to compensate for channel loss in wireline communication, but they have limitations in terms of noise boosting and timing constraints. On the other hand, the forward-backward algorithm can achieve better BER performance, but its high complexity makes it impractical for wireline communication. In this work, we propose a neural network structure that effectively mimics the forward-backward algorithm that performs better than FFE and DFE while reducing complexity compared to the forward-backward algorithm.
서울특별시 관악구 관악로1 서울대학교 반도체공동연구소 설계연구관 (104-1동) 216호 | 02-871-3986
Inter-University Semiconductor Research Center, Building 104-1, Room 216, 1 Gwanak-ro, Gwanak-gu, Seoul, Republic of Korea
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