Hyunwook

Hyunwook Park

Signal and Power Integrity Engineer,

Google LLC

100 W Caribbean Dr, Sunnyvale, CA 94089

Scholar Linkedin

Resume_Hyunwookpark_05-2026.pdf

QUALIFICATION

Signal integrity (SI): High-speed channel design, Frequency and time-domain analysis, Serial (Ethernet, PCIe, HDMI, etc.) and memory interfaces, Connector/cable design, Equalizers, PAM-N signaling, IBIS-AMI, Measurement
Power integrity (PI): Hierarchical PDN analysis (VRM, PCB, PKG, interposer, chip), IR drop, Decoupling capacitor strategy, PWL simulation, Power supply induced jitter (PSIJ), Measurement using VNA and scope
Packaging: 2.5-D ICs for hetero-integration, High bandwidth memory (HBM), Silicon/RDL interposer SI/PI design
Machine learning: SI/PI tool, Design automation, Optimization, DNN, Large language models, Reinforcement learning

WORK EXPERIENCE

May 2026 ~ Present

Sr. Signal and Power Integrity Engineer

TPU Hardware, Google LLC, Sunnyvale, CA, USA

Jun. 2025 ~ May. 2026

ASIC Engineering Tech Lead

SiliconOne, Cisco Systems Inc., San Jose, CA, USA

Jun. 2023 ~ May. 2025

Post-doctoral Fellow

EMC Lab, Dept. Electrical and Computer Engineering, Missouri University Science and Technology (MST), Rolla, MO, USA

Sep. 2022 ~ Feb. 2023

Post-doctoral Researcher

TERA Lab, Dept. Electrical Engineering. Korea Institute Science and Technology (KAIST), Daejeon, South Korea

May. 2021 ~ Feb. 2023

SI/PI Technical Consultant

Analog Device Inc. (ADI), San Jose, CA, USA (Remote)

Sep. 2019 ~ Aug. 2020

SI/PI Technical Consultant

Invecas Inc., Santa Clara, CA, USA (Remote)

Mar. 2017 ~ Aug. 2022

Graduate Research Assistant

TERA Lab, Dept. Electrical Engineering, KAIST, Daejeon, South Korea

PROJECT EXPERIENCE

Google LLC (Sunnyvale, CA, USA) (May. 2026 ~ Present, full-time, on-site)

CISCO SYSTEMS (San Jose, CA, USA) (Jun. 2025 ~ May. 2026, full-time, on-site)

SI/PI Design of AI-scale 102.4 Tbps Switch ASIC (Jun 2025 ~ May 2026)

224 Gbps SerDes SI/PI design including PKG substrate and RDL interposer
RDL interposer channel design for 18 Gbps D2D interface

Surface Roughness Characterization for 200G+ Channel Modeling (Jun 2025 ~ Nov 2025)

Huray model parameter extraction based on measurement

MST (Rolla, MO, USA) (Jun. 2023 ~ May. 2025, full-time, on-site)

PCB Stack-up Design Tool Development using Large Language Models (LLMs) (Jun 2023 ~ May 2025)

Sponsored by LG Electronics Inc., Korea

Equivalent circuit modeling of frequency-dependent resistance and inductance of litz-wire coil for PTE evaluation
Measurement of IH system including coil and SUS load using impedance analyzer and oscilloscope
Development of an automated coil generator GUI tool utilizing ANSYS Maxwell

TECHNICAL SKILLS

EM Simulation tool: ANSYS HFSS/SIWave/Q2D/Q3D/Maxwell | Cadence PowerSI/PowerDC
Circuit Simulation Tools: Keysight ADS | Synopsys HSPICE
Design Tools: Cadence Allegro/APD | Mentor PADS
Equipment: VNA | Digital Oscilloscope | TDR | Impedance Analyzer | Spectrum Analyzer | BERTScope | Micro-probe
Programming & AI: Python | MATLAB | Antigravity | Claude Code | Cursor AI

AWARDS (14)

Best Paper Award of DesignCon 2024

- H. Park et al., “Practical SI EM Simulator using Neural Language Models”

Best SIPI Paper Award of IEEE International Symposium on Electromagnetic Compatibility, Signal Integrity & Power Integrity (EMC+SIPI) 2023

- H. Park et al., “Power Supply Induced Jitter (PSIJ) Modeling, Analysis, and Optimization of High Bandwidth Memory (HBM) I/O Interface”

Best Poster Award of IEEE Electrical Performance of Electronic Packaging and Systems (EPEPS) Conference 2022

- H. Park et al., “Scalable Transformer Network-based Reinforcement Learning Method for PSIJ Optimization in HBM”

Best Paper Award of DesignCon 2025

- T. Shin, H. Park, B. Sim, K. Kim, K. Son, J. Park, H. Kim, H. An, J. Yoon, and J. Kim, “PSIJ Based Integrated Power Integrity Design for HBM Using Reinforcement Learning: Beyond the Target Impedance ”

Best Poster Award of IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Conference 2022

- H. Kim, H. Kim, J. Park, K. Son, H. Park, T. Shin, K. Kim, J. Yoon, J. Lee, J. Hong, J. Kim, and J. Kim, “Design and Analysis of Hierarchical Power Distribution Network (PDN) for Full Wafer Scale Chip (FWSC) Module”

Best Paper Award of DesignCon 2022

- S. Kim, H. Park, T. Shin, D. Lho, K. Son, K. Kim, M. Kim, J. Park and J. Kim, “A Processing-In-memory on High-bandwidth Memory (PIM-HBM): Impact of Interconnect Channels on System Performance in 2.5D/3D IC”

Best Paper Award of DesignCon 2022

- T. Shin, H. Park, S. Kim, K. Kim, K. Son and J. Kim, “A New Challenge for Neuromorphic Computing Systems: From Off-chip Interconnects to On-chip Interconnects”

Best Paper Award of DesignCon 2022

- S. Choi, M. Kim, H. Park, H. Kim, J. Park, J. Kim, K. Kim, D. Lho, J. Yoon, J. Song, K. Kim, J. Park and J. Kim, “Deep Reinforcement Learning-based Channel Flexible Equalization Scheme: An Application to High Bandwidth Memory”

Best Paper Award of DesignCon 2022

- H. Kim, M. Kim, S. Kim, H. Park, and J. Kim, “Imitate Expert Policy & Learn Beyond: A Practical PDN Optimizer by Imitation Learning”

Best Paper Award of IEEE EDAPS Conference 2021

- T. Shin, H. Park, K. Kim, S. Kim, K. Son, K. Son, G. Park, J. Park, S. Choi and J. Kim, “Modeling and Analysis of System-Level Power Supply Noise Induced Jitter (PSIJ) for 4 Gbps High Bandwidth Memory (HBM) I/O Interface”

Best SIPI Paper Award (2nd Place) of IEEE International Symposium on Electromagnetic Compatibility, Signal Integrity & Power Integrity (EMC+SIPI) 2021

- S. Kim, S. Jeong, B. Sim, S. Lee, H. Park, H. Kim, and J. Kim, “Design and Analysis of On-Package Inductor of an Integrated Voltage Regulator for High-Q Factor and EMI Shielding in Active Interposer based 2.5D/3D ICs”

Best Paper Award of DesignCon 2021

- M. Kim, H. Park, S. Choi, K. Kim, S. Kim, S. Kim, D. Lho, K. Son, K, Son, H. Kim and J. Kim, “Neural Language Model Enables Extremely Fast & Robust Routing on Interposer”

Best Student Paper Award of IEEE EDAPS Conference 2020

- K. Son, M. Kim, H. Park, S. Park, G. Park, D. Lho, S. Kim, T. Shin, K. Son, K. Kim and J. Kim, “Deep Reinforcement Learning-based Interconnection Design for 3D X-Point Array Structure Considering Signal Integrity”

Best Student Paper Award of IEEE EDAPS Conference 2019

- G. Park, K. Cho, K. Son, H. Park, D. Lho, S. Kim, T. Shin, T. Kim, A. Watanabee, P. Raj, V. Sundaram, R. Tummala and J. Kim, "Design and Measurement of a 28 GHz Glass Band Pass Filter based on Glass Interposers for 5G Applications"

EDUCATION

Feb. 2019 ~ Aug. 2022

Ph. D. in Dept. Electrical Engineering, KAIST, Daejeon, South Korea (Advisor: Prof. Joungho Kim)

- Thesis: Transformer network-based reinforcement learning method for optimization of power distribution network (PDN) of high bandwidth memory (HBM)

Feb. 2017 ~ Feb. 2019

M. S. in Dept. Electrical Engineering, KAIST, Daejeon, South Korea (Advisor: Prof. Joungho Kim)

- Thesis: Deep reinforcement learning-based optimal decoupling capacitor design method for 2.5-D/3-D ICs

Feb. 2012 ~ Feb. 2017

B. S. in Dept. Electrical Engineering, KAIST, Daejeon, South Korea

PROFESSIONAL ACTIVITIES & MEMBERSHIPS

Reviewer, IEEE Transactions (TEMC, TSIPI, TCPMT, TCAD, TCAS-I), IEEE Conferences (EMC+SIPI 2025, 2024, 2023, APEMC 2024, 2021, 2020, 2019)
Standard activities, HDMI Forum, specialized in connectors and cables (08/2021~02/2023)
IEEE Member, IEEE EMC Society

PUBLICATIONS

Journals (20)

H. Park et al., “High-speed Channel Modeling using Transformer Network,” in IEEE Transactions on Signal Integrity and Power Integrity, 2025.
H. Park et al., “High-Speed Channel Transformer: A Scalable Transformer Network-Based Signal Integrity Simulator,” in IEEE Transactions on Electromagnetic Compatibility, vol. 66, no. 6, pp. 1977-1987, Dec. 2024.
H. Park et al., "Transformer Network-Based Reinforcement Learning Method for Power Distribution Network (PDN) Optimization of High Bandwidth Memory (HBM)," in IEEE Transactions on Microwave Theory and Techniques, vol. 70, no. 11, pp. 4772-4786, Nov. 2022
H. Park et al., "Deep Reinforcement Learning-Based Optimal Decoupling Capacitor Design Method for Silicon Interposer-Based 2.5-D/3-D ICs," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 3, pp. 467-478, March 2020.
D. Kharshiladze, Y. Ding, H. Park, M. Mousavi, N. Bondarenko, H. Ye, F. Smith, B. Achkir, and C. Hwang, "Fast Estimation of Frequency Response for Full-Channel via-Trace Structures up to 60 GHz," in IEEE Transactions on Signal and Power Integrity, vol. 5, pp. 10-21, 2026.
K. Kim, H. Park, S. Kim, Y. Kim, K. Son, D. Lho, K. Son, T. Shin, B. Sim, J. Park, S. Park, and J. Kim, "Policy-Based Reinforcement Learning for Through Silicon Via Array Design in High-Bandwidth Memory Considering Signal Integrity," in IEEE Transactions on Electromagnetic Compatibility, vol. 66, no. 1, pp. 256-269, Feb. 2024.
J. Kim, M. Kim, H. Kim, H. Park, S. Choi, J. Park, B. Sim, K. Son, S. Kim, J. Song, Y. Kim, and J. Kim, "Bayesian Exploration Imitation Learning-Based Contextual via Design Optimization Method of PAM-4-Based High-Speed Serial Link," in IEEE Transactions on Electromagnetic Compatibility, vol. 65, no. 6, pp. 1751-1762, Dec. 2023.
S. Choi, K. Son, H. Park, S. Kim, B. Sim, J. Kim, J. Park, M. Kim, H. Kim, J. Song, Y. Kim, and J. Kim, "Deep Reinforcement Learning-Based Optimal and Fast Hybrid Equalizer Design Method for High-Bandwidth Memory (HBM) Module," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 13, no. 11, pp. 1804-1816, Nov. 2023.
B. Sim, T. Shin, H. Park, K. Son, K. Kim, D. Lho, S. Kim, J. Yoon, H. Kim, J. Lee, J. Kim, and J. Kim, "Fast and Accurate Computation of Wireless Power Transfer System Optimal Design Using Particle Swarm Optimization Method," in IEEE Transactions on Electromagnetic Compatibility, vol. 65, no. 6, pp. 1674-1683, Dec. 2023.
S. Jeong, T. Kim, S. Lee, B. Sim, H. Park, K. Son, S. Kim, T. Shin, Y. Kim, J. Kim, and B. Kim, "Analysis of Repetitive Bending on Flexible Wireless Power Transfer (WPT) PCB Coils for Flexible Wearable Devices," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 11, pp. 1748-1756, Nov. 2022.
K. Son, S. Kim, H. Park, T. Shin, K. Kim, M. Kim, B. Sim, S. Kim, G. Park, S. Park, S. Jeong and J. Kim, "Thermal and Signal Integrity Co-Design and Verification of Embedded Cooling Structure With Thermal Transmission Line for High Bandwidth Memory Module," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 9, pp. 1542-1556, Sept. 2022.
D. Lho, H. Park, S. Park, S. Kim, H. Kang, B. Sim, S. Kim, J. Park, K. Cho, J. Song, Y. Kim and J. Kim, "Channel Characteristic-Based Deep Neural Network Models for Accurate Eye Diagram Estimation in High Bandwidth Memory (HBM) Silicon Interposer," in IEEE Transactions on Electromagnetic Compatibility, vol. 64, no. 1, pp. 196-208, Feb. 2022.
K. Son, M. Kim, H. Park, D. Lho, K. Son, K. Kim, S. Lee, S. Jeong, S. Park, S. Hong, G Park and J. Kim, "Reinforcement-Learning-Based Signal Integrity Optimization and Analysis of a Scalable 3-D X-Point Array Structure," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 1, pp. 100-110, Jan. 2022.
S. Kim, S. Kim, K. Cho, T. Shin, H. Park, D. Lho, S. Park, K. Son, G. Park, S. Jung, Y. Kim and J. Kim, "Signal Integrity and Computing Performance Analysis of a Processing-In-Memory of High Bandwidth Memory (PIM-HBM) Scheme," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 11, pp. 1955-1970, Nov. 2021.
T. Shin, S. Park, S. Kim, S. Kim, K. Son, H. Park, D. Lho, K. Cho, G. Park, K. Gong, S. Jeong and J. Kim, "Signal Integrity Modeling and Analysis of Large-Scale Memristor Crossbar Array in a High-Speed Neuromorphic System for Deep Neural Network," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 7, pp. 1122-1136, July 2021.
G. Park, Y. Kim, K. Cho, J. Park, I. Hwang, J. Kim, K. Son, H. Park, A. Watanabe, P. Raj, R. Tummala and J. Kim, "Measurement and Analysis of Through Glass Via Noise Coupling and Shielding Structures in a Glass Interposer," in IEEE Transactions on Electromagnetic Compatibility, vol. 63, no. 5, pp. 1562-1573, Oct. 2021.
B. Sim, S. Jeong, Y. Kim, S. Park, S. Lee, S. Hong, J. Song, H. Kim, H. Kang, H. Park, D. Lho and J. Kim, "A Near Field Analytical Model for EMI Reduction and Efficiency Enhancement Using an nth Harmonic Frequency Shielding Coil in a Loosely Coupled Automotive WPT System," in IEEE Transactions on Electromagnetic Compatibility, vol. 63, no. 3, pp. 935-946, June 2021.
Y. Kim, Fujimoto, S. Kaji, S. Wada, H. Park, D. Lho, J. Kim and Y. Hayashi, “Segmentation method based modeling and analysis of a glass package power distribution network (PDN)”, in Nonlinear Theory and Its Applications, IEICE, vol. 11, no. 2, p. 170-188, 2020.
J. Park, S. Park, Y. Kim, G. Park, H. Park, D. Lho, K. Cho, S. Lee, D. Kim and J. Kim, "Polynomial Model-Based Eye Diagram Estimation Methods for LFSR-Based Bit Streams in PRBS Test and Scrambling," in IEEE Transactions on Electromagnetic Compatibility, vol. 61, no. 6, pp. 1867-1875, Dec. 2019.
K. Cho, Y. Kim, S. Kim, H. Park, J. Park, S. Lee, D. Shim, K. Lee, H. Kim, S. Oh and J. Kim, "Fast and Accurate Power Distribution Network Modeling of a Silicon Interposer for 2.5-D/3-D ICs With Multiarray TSVs," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 9, pp. 1835-1846, Sept. 2019.

Conferences (80)

H. Park et al., “Differential Via Modeling using Multilayer Perceptron-Sequential (MLP-SEQ) Neural Network,” IEEE EMC+SIPI, 2025.
H. Park et al., “Data Representation and Preprocessing Effects on S-parameter Modeling of High-speed Channels using Machine Learning,” IEEE EMC+SIPI, 2025.
H. Park et al., "High-speed Channel Simulator using Neural Language Models," 2024 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI), Phoenix, AZ, USA, 2024, pp. 11-16.
H. Park et al., “Practical SI EM Simulator using Neural Language Models,” in Proc. DesignCon, Santa Clara, CA, USA, Jan. 2024.
H. Park et al., “Power Supply Induced Jitter (PSIJ) Modeling, Analysis, and Optimization of High Bandwidth Memory (HBM) I/O Interface,” 2023 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI).
H. Park et al., “Scalable Transformer Network-based Reinforcement Learning Method for PSIJ Optimization in HBM,” 2022 IEEE 31th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2022, pp. 1-3.
H. Park et al., “Signal Integrity Design and Analysis of a HDMI 2.1 Connector for Improved Electrical Characteristics,” 2021 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2021, pp. 1-3.
H. Park et al., “Crosstalk-included PAM-4 Worst Eye Diagram Estimation Method for High-speed Serial Links,” 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021, pp. 1-3.
H. Park et al., "Policy Gradient Reinforcement Learning-based Optimal Decoupling Capacitor Design Method for 2.5-D/3-D ICs using Transformer Network," 2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2020, pp. 1-3.
H. Park et al., "Fast and Accurate Deep Neural Network (DNN) Model Extension Method for Signal Integrity (SI) Applications," 2019 Electrical Design of Advanced Packaging and Systems (EDAPS), KAOHSIUNG, Taiwan, 2019, pp. 1-3.
H. Park et al., "Reinforcement Learning-Based Optimal On-board Decoupling Capacitor Design Method," 2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, 2018, pp. 213-215.
S. Jeong, H. Park, and H. Wang, "Extraction of Surface Roughness and Dielectric Properties for High-Speed Digital Channels using Bayesian Optimization," 2026 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI).
D. Kharshiladze, H. Park, Z. Yang and C. Hwang, "Boosting High-Speed Channel Transformer Performance with Gating Neural Network," 2026 IEEE 30th Workshop on Signal and Power Integrity (SPI), Turin, Italy, 2026, pp. 1-4.
Y. Zhang, L. Zhang, H. Park, B. Pu, X. Cai, C. Hwang, B. Sen, J. Fan, E. Li, and J. Drewniak, "Multi-Objective Inverse Optimization of High-Speed Interconnects Using Cascaded Deep Neural Network," 2025 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI), Raleigh, NC, USA, 2025, pp. 120-125.
K. Kim, T. Shin, H. Park, S. Choi, H. Kim, J. Lee, H. An, K. Son, H. Suh, W. Choi, and J. Kim, "Large Language Model-Based Decoupling Capacitor Placement Optimization," 2025 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI), Raleigh, NC, USA, 2025, pp. 291-296.
T. Shin, H. Park, B. Sim, K. Kim, K. Son, J. Park, H. Kim, H. An, J. Yoon, and J. Kim, “PSIJ-based Integrated Power Integrity Design for HBM using Reinforcement Learning: Beyond the Target Impedance” in Proc. DesignCon, Santa Clara, CA, USA, Jan. 2025.
K. Kim, H. Park, K. Son, S. Choi, T. Shin, J. Lee, J. Yoon, H. Ahn, H. Kim, W. Choi, J. Choi, and J. Kim, "Explainable Reinforcement Learning(XRL)-Based Decap Placement Optimization for High Bandwidth Memory (HBM)," 2024 IEEE 33rd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Toronto, ON, Canada, 2024, pp. 1-3.
T. Shin, K. Kim, H. Park, B. Sim, S. Kim, J. Kim, S. Choi, J. Park, J. Song , J. Kim, J. Park, D. Kang, and J. Kim, “Signal Integrity Design and Analysis of Universal Chiplet Interconnect Express (UCIe) Channel in Silicon Interposer for Advanced Package”, 2023 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), Rose-Hill, Mauritius 2023, pp. 1-3.
S. Kim, K. Son, J. Yoon, T. Shin, K. Kim, B. Sim, J. Park, S. Choi, J. Kim, H. Kim, H. Park, and J. Kim, “Signal Integrity Analysis of High-speed PCIe Channel with Board-to-Board Interconnect for High-Performance Server,” 2023 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), Rose-Hill, Mauritius, 2023, pp. 1-3.
J. Yoon, H. Kim, B. Sim, H. Park, Y. Kim, S. Park, Y. Kwon, and J. Kim, "Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect," 2023 20th International SoC Design Conference (ISOCC), Jeju, Korea, Republic of, 2023, pp. 247-248.
J. Yoon, H. Park, H. Kim, B. Sim, J. Hong, S. Kim, K. Son, K. Kim, Y. Kim, S. Park, Y. Kwon, and J. Kim, "Design and Analysis of Redistribution Layer Interposer Channel Considering Signal Integrity for High Bandwidth Memory Module," 2023 IEEE 32nd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Milpitas, CA, USA, 2023, pp. 1-3.
T. Shin, H. Park, D. Lho, K. Kim, B. Sim, S. Kim, J. Kim, S. Choi, J. Yoon, J. Song, S. Chun, and J. Kim, “SI/PI Co-Design of 12.8 Gbps HBM I/O Interface using Bayesian Optimization for PSIJ Reduction,” 2023 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI).
B. Sim, T. Shin, H. Park, K. Son, K. Kim, D. Lho, H. Kang, J. Park, H. Kim, J. Kim, S. Choi, and J. Kim, "Bayesian Optimization based Fast and Accurate Wireless Power Transfer System Coil Optimization for High Efficiency," 2023 IEEE Wireless Power Technology Conference and Expo (WPTCE), San Diego, CA, USA, 2023, pp. 1-5.
S. Choi, J. Kim, M. Kim, H. Park, H. Kim, J. Park, K. Son, S. Kim, T. Shin, K. Kim, J. Yoon, J. Song, K. Kim, J. Park, and J. Kim, “Extremely Fast Dynamic Link Equalization for PCIe based on Imitation Learning,” in Proc. DesignCon, Santa Clara, CA, USA, Jan. 2023.
K. Son, D. Lho, K. Kim, S. Choi, H. Kim, H. Park, B. Sim, H. Kim, T. Shin, and J. Kim, "Power Distribution Network Impedance Analysis considering Thermal Distribution," 2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), Urbana, IL, USA, 2022, pp. 1-3.
H. Kim, H. Kim, J. Park, K. Son, H. Park, T. Shin, K. Kim, J. Yoon, J. Lee, J. Hong, J. Kim, and J. Kim, "Design and Analysis of Hierarchical Power Distribution Network (PDN) for Full Wafer Scale Chip (FWSC) Module," 2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), Urbana, IL, USA, 2022, pp. 1-3.
D. Lho, H. Park, K. Kim, S. Kim, B. Sim, K. Son, K. Son, J. Kim, S. Choi, J. Park, H. Kim, K. Kong and J. Kim, “Deterministic Policy Gradient-based Reinforcement Learning for DDR5 Memory Signaling Architecture Optimization considering Signal Integrity,” 2022 IEEE 31th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2022, pp. 1-3.
B. Sim, K. Kim, T. Shin, H. Park, S. Kim, D. Lho, K. Son, K. Kong, S. Jeong, S. Choi, J. Kim and J. Kim, “Intra-pair Skew Impact Analysis of High-speed Cables for HDMI Interface,” 2022 IEEE 31th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2022, pp. 1-3.
K. Son, K. Kim, G. Park, D. Lho, H. Park, B. Sim, T. Shin, J. Park, H. Kim and J. Kim, “Signal Integrity and Power Leakage Optimization for 3D X-Point Memory Operation using Reinforcement Learning,” 2022 IEEE 31th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2022, pp. 1-3.
S. Kim, H. Park, T. Shin, D. Lho, K. Son, K. Kim, M. Kim, J. Park and J. Kim, “A Processing-In-memory on High-bandwidth Memory (PIM-HBM): Impact of Interconnect Channels on System Performance in 2.5D/3D IC,” in Proc. DesignCon, Santa Clara, CA, USA, Apr. 2022.
T. Shin, H. Park, S. Kim, K. Kim, K. Son and J. Kim, “A New Challenge for Neuromorphic Computing Systems: From Off-chip Interconnects to On-chip Interconnects,” in Proc. DesignCon, Santa Clara, CA, USA, Apr. 2022.
K. Son, K. Kim, M. Kim, T. Shin, H. Park, S. Kim, S. Choi, J. Park, J. Kim, H. Kim and J. Kim, “Thermal Transmission Line: Smoothing Thermal Gradients & Lowering Temperature for Signal Integrity Improvement of HBM & 2.5D ICs,” in Proc. DesignCon, Santa Clara, CA, USA, Apr. 2022.
H. Kim, M. Kim, S. Kim, H. Park, and J. Kim, “Imitate Expert Policy & Learn Beyond: A Practical PDN Optimizer by Imitation Learning,” in Proc. DesignCon, Santa Clara, CA, USA, Apr. 2022.
J. Park, M. Kim, S. Choi, J. Kim, H. Kim, H. Park, S. Kim, T. Shin and J. Kim, “Learning Super-scale Microbump Pin Assignment Optimization for Real-world PCB Design with Graph Representation,” in Proc. DesignCon, Santa Clara, CA, USA, Apr. 2022.
J. Kim, M. Kim, H. Park, J. Yoon, S. Choi, J. Park, H. Kim, K. Son, S. Kim, D. Lho, K. Kim, J. Song, K. Kim, J. Park and J. Kim, “Imitation Learning with Bayesian Exploration (IL-BE) for Signal Integrity (SI) of PAM-4 based High-speed Serial Link: PCIe 6.0,” in Proc. DesignCon, Santa Clara, CA, USA, Apr. 2022.
S. Choi, M. Kim, H. Park, H. Kim, J. Park, J. Kim, K. Kim, D. Lho, J. Yoon, J. Song, K. Kim, J. Park and J. Kim, “Deep Reinforcement Learning-based Channel Flexible Equalization Scheme: An Application to High Bandwidth Memory,” in Proc. DesignCon, Santa Clara, CA, USA, Apr. 2022.
T. Shin, H. Park, K. Kim, S. Kim, K. Son, K. Son, G. Park, J. Park, S. Choi and J. Kim, “Modeling and Analysis of System-Level Power Supply Noise Jitter (PSIJ) for 4 Gbps High Bandwidth Memory (HBM) I/O Interface,” 2021 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2021, pp. 1-3.
S. Kim, T. Shin, H. Park, D. Lho, K. Son, K. Kim, J. Park, S. Choi, J. Kim, H. Kim and J. Kim, “Signal Integrity Design and Analysis of a Spiral Through-Silicon Via (TSV) Array Channel for High Bandwidth Memory (HBM),” 2021 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2021, pp. 1-3.
M. Kim, H. Park, K. Son, S. Kim, H. Kim, J. Kim, J. Song, Y. Gu, J. Park and J. Kim, “Imitation Learning for Simultaneous Escape Routing,” 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021, pp. 1-3.
J. Kim, H. Park, M. Kim, S. Kim, S. Choi, K. Son, J. Park, H. Kim, J. Song, Y. Ku, J. Park and J. Kim, “PAM-4 based PCIe 6.0 Channel Design Optimization Method using Bayesian Optimization,” 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021, pp. 1-3.
D. Lho, H. Park, G. Park, J. Park, K. Son, B. Sim, H. Kang, S. Kim, T. Shin, K. Kim, K. Son, J. Kim and J. Kim, “Design and Analysis of HDMI 2.1 Connector for Crosstalk Reduction using Tabs and Inverse Tabs,” 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021, pp. 1-3.
H. Kim, H. Park, M. Kim, S. Choi, J. Kim, J. Park, S. Kim, S. Kim and J. Kim, “Deep Reinforcement Learning Framework for Optimal Decoupling Capacitor Placement on General PDN with an Arbitrary Probing Port,” 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021, pp. 1-3.
S. Choi, M. Kim, H. Park, K. Son, S. Kim, J. Kim, J. Park, H. Kim, T. Shin, K. Kim and J. Kim, “Sequential Policy Network-based Optimal Passive Equalizer Design for Arbitrary Channel of High Bandwidth Memory using Advantage Actor Critic,” 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021, pp. 1-3.
J. Park, M. Kim, S. Kim, K. Son, T. Shin, H. Park, J. Kim, S. Choi, H. Kim, K. Kim and J. Kim, “Deep Reinforcement Learning-based Pin Assignment Optimization of BGA Packages considering Signal Integrity with Graph Representation,” 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021, pp. 1-3.
K. Son, S. Kim, M. Kim, D. Lho, K. Kim, H. Park, G. Park and J. Kim, “Signal Integrity Analysis of High Speed Channel considering Thermal Distribution,” 2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2021, pp. 1-3.
S. Kim, S. Jeong, B. Sim, S. Lee, H. Park, H. Kim and J. Kim, “Design and Analysis of On-package Inductor of an Integrated Voltage Regulator for High-Q Factor and EMI Shielding in Active Interposer Based 2.5D/3D ICs,” 2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposium, 2021, pp. 498-503.
K. Kong, H. Park, S. Kim, K. Son, B. Sim and J. Kim, “A New Design Method of GDDR6 WCLK Using Reinforcement Learning for over 20Gbps,” in Proc. DesignCon, Santa Clara, CA, USA, Aug. 2021.
M. Kim, H. Park, S. Choi, K. Kim, S. Kim, S. Kim, D. Lho, K. Son, K, Son, H. Kim and J. Kim, “Neural Language Model Enables Extremely Fast & Robust Routing on Interposer,” in Proc. DesignCon, Santa Clara, CA, USA, Aug. 2021.
S. Kim, G. Park, S. Jeong, S. Kim, H. Park and J. Kim, “Wireless Memory Test: A Breakthrough Solution or Highly Reliable HBM,” in Proc. DesignCon, Santa Clara, CA, USA, Aug. 2021.
K. Kim, H. Park, D. Lho, M. Kim, K. Son, K. Son, S. Kim, T. Shin and J. Kim, "Deep Reinforcement Learning-based Through Silicon Via (TSV) Array Design Optimization Method considering Crosstalk," 2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2020, pp. 1-3.
G. Park, H. Park, D. Lho, J. Park, K. Son, S. Kim, T. Shin, K. Son, J. Park, J. Kim, J. Lee and S. Choi, "Design and Measurement of a HDMI 2.1 Connector for 8K TV considering Signal Integrity," 2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2020, pp. 1-3.
D. Lho, H. Park, S. Kim, T. Shin, K. Kim, K. Son, H. Kang, B. Sim, K. Son, M. Kim and J. Kim, "Deep Neural Network-based Lumped Circuit Modeling using Impedance Curve," 2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2020, pp. 1-3.
K. Son, M. Kim, H. Park, S. Park, G. Park, D. Lho, S. Kim, T. Shin, K. Son, K. Kim and J. Kim, "Deep Reinforcement Learning-based Interconnection Design for 3D X-Point Array Structure Considering Signal Integrity," 2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2020, pp. 1-3.
K. Son, S. Kim, S. Park, H. Park, K. Kim, T. Shin, M. Kim, K. Son, G. Park, S. Jeong and J. Kim, "Design and Analysis of Thermal Transmission Line based Embedded Cooling Structures for High Bandwidth Memory Module and 2.5D/3D ICs," 2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 2020, pp. 1-3.
B. Sim, D. Lho, D. Park, S. Jeong, S. Lee, H. Kim, H. Park, H. Kang, S. Hong and J. Kim, "A Deep Neural Network-based Estimation of Efficiency Enhancement by an Intermediate Coil in Automotive Wireless Power Transfer System," 2020 IEEE Wireless Power Transfer Conference (WPTC), 2020, pp. 231-233.
K. Kim, D. Lho, H. Park, K. Son, S. Kim, S. Park, B. Sim, S. Kim and J. Kim, "Convolutional Neural Network-based Fast and Accurate Irregular Shape Power/Ground Plane Impedance Estimation Method for High-Speed Signaling," 2020 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), 2020, pp. 1-3.
K. Son, S. Kim, H. Park, S. Kim, K. Kim, S. Park, B. Sim, S. Jeong, G. Park and J. Kim, "A Novel Through Mold Plate (TMP) for Signal and Thermal Integrity Improvement of High Bandwidth Memory (HBM)," 2020 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), 2020, pp. 1-4.
M. Kim, H. Park, S. Kim, K. Son, S. Kim, K. Son, S. Choi, G. Park and J. Kim, "Reinforcement Learning-based Auto-router considering Signal Integrity," 2020 IEEE 29th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, USA, 2020, pp. 1-3.
S. Jeong, S. Lee, S. Hong, B. Sim, H. Park, S. Kim, Y. Kim, K. Son, J. Lee, J. Don and J. Kim, "Design, Simulation and Measurement of a Flexible Voltage-controlled Oscillator (VCO) Chip with Bending Radius," 2020 IEEE 29th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, USA, 2020, pp. 1-4.
B. Sim, D. Lho, D. Park, H. Park, H. Kang and J. Kim, "A Deep Neural Network-based Estimation of EMI Reduction by an Intermediate Coil in Automotive Wireless Power Transfer System," 2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), Reno, NV, USA, 2020, pp. 407-410
T. Shin, S. Park, S. Kim, H. Park, D. Lho, S. Kim, K. Son, G. Park and J. Kim, "Modeling and Demonstration of Hardware-based Deep Neural Network (DNN) Inference using Memristor Crossbar Array considering Signal Integrity," 2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), Reno, NV, USA, 2020, pp. 417-421
H. Kang, D. Lho, H. Park, T. Kong, H. Choi and J. Kim, "An Induction Heating System Analysis Method based on Operating Conditions," 2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), Reno, NV, USA, 2020, pp. 478-481
S. Kim, K. Cho, S. Park, H. Park, G. Park, S. Jeong and J. Kim, “Integrated Voltage Regulator on Active Interposer for Power Noise Suppression in 3D AI Computing System,” in Proc. DesignCon, Santa Clara, CA, USA, Jan. 2020.
Y. Kim, Y. Hayashi, F. Daisuke, H. Park and J. Kim, “Statistical Signal/Power Integrity Analysis of High-Bandwidth Memory (HBM) Interposer Channel Considering SSO Noise and Data Coding,” in Proc. DesignCon, Santa Clara, CA, USA, Jan. 2020.
G. Park, K. Cho, K. Son, H. Park, D. Lho, S. Kim, T. Shin, T. Kim, A. Watanabe, P. Raj, V. Sundaram, R. Tummala and J. Kim, "Design and Measurement of a 28 GHz Glass Band Pass Filter based on Glass Interposers for 5G Applications," 2019 Electrical Design of Advanced Packaging and Systems (EDAPS), KAOHSIUNG, Taiwan, 2019, pp. 1-3.
S. Kim, K. Cho, S. Park, H. Park, S. Kim, S. Jeong, K. Son and J. Kim, "Power Integrity Comparison of Off-chip, On-interposer, On-chip Voltage Regulators in 2.5D/3D ICs," 2019 Electrical Design of Advanced Packaging and Systems (EDAPS), KAOHSIUNG, Taiwan, 2019, pp. 1-3.
H. Kang, S. Kim, D. Lho, H. Park, B. Sim and J. Kim, "Noise Coupling Analysis Method for an Electronic Safety and Arming Device (ESAD)," 2019 Electrical Design of Advanced Packaging and Systems (EDAPS), KAOHSIUNG, Taiwan, 2019, pp. 1-3.
G. Kumar, G. Park, H. Park, D. Lho, J. Park, J. Lee, S. Choi and J. Kim, "Design and Analysis of High-Definition Multimedia Interface Connectors considering Signal Integrity," 2019 Electrical Design of Advanced Packaging and Systems (EDAPS), KAOHSIUNG, Taiwan, 2019, pp. 1-3.
S. Jeong, S. Lee, B. Sim, S. Hong, H. Park, S. Kim and J. Kim, "Modeling, Simulation and Measurement of On-chip Interconnects with Extremely Thin Si Substrate for Flexible Electronics," 2019 Electrical Design of Advanced Packaging and Systems (EDAPS), KAOHSIUNG, Taiwan, 2019, pp. 1-3.
Y. Kim, D. Fujimoto, H. Nishiyama, Y. Hayashi, D. Lho, H. Park and J. Kim, "Statistical Analysis of Simultaneous Switching Output (SSO) Impacts on Steady State Output Responses and Signal Integrity," 2019 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo), Hangzhou, China, 2019, pp. 138-140.
S. Kim, S. Kim, K. Cho, T. Shin, H. Park, D. Lho, S. Park, K. Son, G. Park, and J. Kim, “Processing-in-memory in High Bandwidth Memory (PIM-HBM) Architecture with Energy-efficient and Low Latency Channels for High Bandwidth System,” 2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, 2018, pp. 213-215.
D. Lho, J. Park, H. Park, S. Park, S. Kim, H. Kang, S. Kim, G. Park, K. Son, and J. Kim, “Bayesian Optimization of High-Speed Channel for Signal Integrity Analysis,” 2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
K. Son, S. Choi, D. Jung, K. Kim, G. Park, D. Lho, H. Park, S. Park, and J. Kim, “Design and Analysis of a 10 Gbps USB 3.2 Gen 2 Type-C Connector for TV Set-Top Box,” 2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
S. Jeong, Y. Kim, S. Park, H. Park, and J. Kim, "Design and Analysis of Flexible Interconnects on an Extremely Thin Silicon Substrate for Flexible Wearable Devices," 2019 Joint International Symposium on Electromagnetic Compatibility, Sapporo and Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Sapporo/APEMC), Sapporo, Japan, 2019, pp. 387-390
J. Park, S. Kim, T. Shin, D. Lho, H. Park, G. Park, and J. Kim, "Eye Diagram Prediction for Input/output Buffer Information Specification-Algorithmic Modeling Interface (IBIS-AMI)," 2019 Joint International Symposium on Electromagnetic Compatibility, Sapporo and Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Sapporo/APEMC), Sapporo, Japan, 2019, pp. 297-300.
J. Park, T. Shin, S. Kim, H. Park, D. Lho, K. Cho, H. Kim, M. Bae, D. Ha, and J. Kim, "Electrical Performance Comparison between Coaxial and Non-coaxial Silicone Rubber Socket," 2019 Joint International Symposium on Electromagnetic Compatibility, Sapporo and Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Sapporo/APEMC), Sapporo, Japan, 2019, pp. 293-296.
K. Cho, Y. Kim, S. Kim, H. Park, J. Park, S. Lee, and J. Kim, "Power Distribution Network (PDN) Modeling of the Perforated Planes in A Silicon Interposer for High Bandwidth Memory (HBM)," 2018 IEICE.
D. Lho, J. Park, H. Park, H. Kang, S. Park and J. Kim, "Eye-Width and Eye-Height Estimation Method Based on Artificial Neural Network (ANN) for USB 3.0," 2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, 2018, pp. 209-211.
S. Kim, Y. Kim, K. Cho, J. Song, S. Park, J. Park, H. Park, S. Jeong and J. Kim, "Design and Analysis of Interposer-Level Integrated Voltage Regulator for Power Noise Suppression in High Bandwidth Memory I/O Interface," 2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, 2018, pp. 159-161.
G. Park, Y. Kim, K. Cho, J. Park, K. Son, H. Park, A. Watanabee, P. Raj, V. Sundaram, R. Tummala and J. Kim, "Design and Analysis of Receiver Channels of Glass Interposers for 5G Small Cell Front End Module," 2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, 2018, pp. 107-109.

PATENTS (2)

U.S Patent (1)

K. Son, J. Kim, S. Kim, S. Park, S. Jeong, G. Park, B. Sim, H. Park, T. Shin, S. Kim, K. Son, M. Kim, “Semiconductor package including embedded cooling structure,” US Patent number: US11990389B2.

South Korea Patent (1)

K. Son, J. Kim, S. Kim, S. Park, S. Jeong, G. Park, B. Sim, H. Park, T. Shin, S. Kim, K. Son, M. Kim, “SEMICONDUCTOR PACKAGE,” South Korea Patent number: KR102553024B1.

INVITED SEMINAR/ LECTURE

IEEE EMC+SIPI Symposium 2024 (Aug. 5-9, 2024)

Held at Phoenix Convention Center, Phoenix, Arizona, USA

- Invited in exemplary paper session (Title: Practical SI EM Simulator using Neural Language Models (DesignCon 2024 paper))

EMC Korea 2022 (Jul. 14, 2022)

Held at Korea Institute of Science and Technology, Seoul, Korea

- Invited as a presenter (Title: Machine Learning-based SI/PI Design for High-speed Digital Systems)

SK Hynix–KAIST: ASK Course (Aug. 26-27, 2020)

Held at KAIST, Daejeon, Korea

- A lecturer for hands-on course (Title: Signal Integrity Design and Simulation of 3-D ICs)

SK Hynix–KAIST: Machine Learning Course (Jul. 30, 2019)

Held at KAIST, Daejeon, Korea

- A lecturer for hands-on course (Title: HBM and Machine Learning for Semiconductor Design)

Lecture at KAIST: AI for High Frequency Circuits, WPT, and Antenna Design (Sep-Dec, 2019)

Held at KAIST, Daejeon, Korea

- A teaching assistant (TA)

Lecture at KAIST: EMC/EMI Design and Analysis (Mar-Jun, 2019)

Held at KAIST, Daejeon, Korea

- A teaching assistant (TA)

Page updated

Google Sites

Report abuse