Hello! I'm B.S student in the school of electronics engineering at KyungPook National University(KNU). 

I'm participated in  AI-S2oC Lab through the AI Soc intensive camp 2024 summer.  

I want to experience the system on chip about AI and microprocessor,  and wanna to build own's career, professional Soc architecture designer.

Low power/high speed Co-operative Hardware-Software  friendly microprocessor architecture.

powerful and efficient new system on chip structure for Parallel Processing using multi-core.

Accelerator with Matrix Reordering Techniques for efficient memory access, based on RISC-V.

 advanced software algorithm to enhance the performance of the system on chip operation.

customized system on chip design from low/simple scale to large/complex scale.

1. Basic Computer architecture and micro-architecture of Arm/AMD/Intel processor.

2. Basic low level Software of Compiler, hardware interface algorithms.

3. Development the practical CNN Accelerator 's memory interface and System algorithms.

4. Implement the practical CNN Accelerator chip.

1. Hoseong Kim and Daejin Park. Low-Power High Speed CNN Accelerator with Matrix Reordering Techniques for Small Footprint Memory Access, In IEEE international Conference on Artificial Intelligence in Information and Communication  (ICAIIC 2025), 2025. 

IEEE international Conference on Artificial Intelligence in Information and Communication, ICAIIC 2025, Fukuoka, Japan