Korean Patent filed 10-2025-0104681 “산화 티타늄 반도체층을 포함하는 수직 적층 메모리 커패시터 및 이의 제조 방법” July. 2025.

Korean Patent filed 10-2025-0210869 “양자우물구조의 채널을 갖는 트랜지스터 및 이를 포함하는 3차원 디램” Dec. 2025.

Korean Patent filed 10-2025-0171019 “자가-정렬된 개구부를 포함하는 반도체 소자 및 이의 제조방법” Nov. 2025. 

Korean Patent filed 10-2025-0113388 “강유전체 절연막 내 oxysen vacancy 조절을 위한 scavenging layer가 포함된 강유전체 터널 정션” Aug. 2025.

Korean Patent filed 10-2024-0102510 “M3D 기술이 활용된 CMOS 삼진 Latchs 위에 비휘발성 메모리 array가 집적된 CMOS 삼진-아이징 머신” Aug. 2024.

Korean Patent filed 10-2024-0095512 “강유전체 분극을 가속시키는 박막을 포함하는 강유전체 메모리” Jul. 2024.

Korean Patent filed 10-2024-0162682 “수직형 hole-type 트랜지스터의 self-align 홀 형성 방법” Nov. 2024.

Korean Patent filed 10-2023-0089070 “이미지 캡쳐 및 뉴럴 프로세싱을 위한 전 처리 기능을 갖는 초 저전력 일체형 이미지 센서” Jul. 2023.

Korean Patent filed 10-2023-0154206 “Staggered Hole 기반 WL Plate를 갖는 0TnC 메모리 기술” Jul. 2023.

Korean Patent filed 10-2023-0154206 “Hole-type vertical 1T1C DRAM” Nov. 2023.

Korean Patent filed 10-2023-0154203 “고성능/고신뢰성 강유전체 메모리 소자” Nov. 2023.

Korean Patent filed 10-2023-0154205 “고성능/고안정성 수직 채널 올어라운드 (CAA) 강유전체 전계효과트랜지스터 (FeFET)” Nov. 2023.

Korean Patent filed 10-2023-0109018 “초고속 동작이 가능한 NAND String 동작 및 아키텍쳐” Aug. 2023.

Korean Patent Application filed 10-2022-0094203 “3진 신경망 가속기 소자 및 그 동작 방법” July 28, 2022.

Korean Patent Application filed 10-2021-0155661 “TCAM 소자 및 그 동작 방법” November 12, 2021.

Korean Patent Application filed 10-2021-0154777 “강유전체 메모리 소자 및 그 제조 방법” November 11, 2021.

Korean Patent Application filed 10-2021-0114033 “강유전체 메모리 소자 및 그 제조 방법” August 27, 2021.

Korean Patent Application filed 10-2021-0099069 “낸드 플래시 메모리 소자의 동작 방법” July 28, 2021.

Korean Patent Application filed 10-2021-0099068 “강유전체 메모리 소자 및 그 제조 방법” July 8, 2021.

Korean Patent Application No. 10-2368866 “Ferroelectric Memory Device and Method of Fabricating the same” February 24, 2022.

Korean Patent Application No. 10-2353462 “Ternary Inverter Device” January 17, 2022.

Korean Patent Application No. 10-2016-0159881 “Tunneling Field Effect Transistor (TFET) based Sensor with Multi Dielectric Gate Stack and Method of Fabricating the same” November 29, 2016.

Korean Patent Application No. 10-1657988 “MULTIPLEXED TUNNEL FIELD-EFFECT TRANSISTOR BIOSENSOR” October 9, 2016

Korean Patent Application No. 10-1658037 “Method of Driving Active Display Device” October 9, 2016.

 Korean Patent Application filed 10-2016-0031861 “Semiconductor Device with Air-Gap Underneath the Active Region and its Fabrication Method” March 17, 2016.

Korean Patent Application filed 10-2016-0031860 “Tunnel Field-Effect Transistor (TFET) with Asymmetric Channel and Gate Dielectric” March 17, 2016.

Korean Patent Application filed 10-2015-0160049 “Method of Initializing 3 Dimensional Non-Volatile Memory Device” November 14, 2015.

Korean Patent Application filed 10-2015-0155418 “Method of Initializing and Programing 3 Dimensional Non-Volatile Memory Device” November 5, 2015.

Korean Patent Application filed 10-2015-0154161 “Method of Initializing and Programing 3 Dimensional Non-Volatile Memory Device” November 3, 2015.

Korean Patent Application filed 10-2015-0018348 “TUNNEL FIELD-EFFECT TRANSISTOR WITH RAISED DRAIN REGION” February 6, 2015.

Korean Patent Application No.10-1195544 “FABRICATION METHOD OF THIN FILM TRANSISTOR WITH ROUNDED GATE,” October 23, 2012.

Korean Patent Application No. 10-1113885 “TWO BIT RRAM USING INVERTED STAGGERED THIN FILM TRANSISTOR STRUCTURE,” February 1, 2012.

Korean Patent Application filed 10-2010-0099542 “Transistors and Electronic Devices including the same,” October 12, 2010.

United States Patent USA 18/303,941 “TERNARY NEURAL NETWORK ACCELERATOR DEVICE AND METHOD OF OPERATING THE SAME,” April 2023. 

United States Patent USA 2024/0186399 A1 “SUPERLATTICE, FERROIC ORDER THIN FILMS FOR USE AS HIGH/NEGATIVE-K DIELECTRIC,” June 2024.

PCT/KR2024/008801 “High Performance NAND String Operation and Architecture,” June 2024.

PCT/KR2025/018673 "자가-정렬된 개구부를 포함하는 반도체 소자 및 이의 제조방법" Nov 2025.

United States Patent No. 9947413B2, entitled “Method of Initializing and Programing 3D Non-Volatile Memory Device,” filed April 17, 2018.

United States Patent No. 10074435B2, entitled “Method of Initializing and Programing 3D Non-Volatile Memory Device,” filed September 11, 2018.

United States Patent No. 9685235B2, entitled “Method of Initializing and Driving 3D Non-Volatile Memory Device Using Time Varying Erase Signal,” filed September 5, 2017.

United States Patent No. 9824759B2, entitled “Non-Volatile Memory Devices, Memory Systems, and Methods of Operating the same” filed January 29, 2015.

United States Patent No. 9123817B2, entitled “Transistors and Electronic Devices including the same,” filed September 1, 2015.

 United States Patent No. 9105235B2, entitled “Methods of Driving Active Display Device,” filed August 11, 2015.