Patents

Probabilistic inference from imprecise knowledge, Radu Marinescu, Haifeng Qian, Debarun Bhattacharjya, Alexander Gray, Francisco Barahona, Tian Gao and Ryan Nelson Riegel, U.S. Patent Application 18/050621, 2022.

Neural Network Robustness through Obfuscation, Mark Wegman, Haifeng Qian, Ian Molloy, Taesung Lee and Chiayi Hsu, U.S. Patent Application 17/036046, 2020.

Dividing Training Data for Aggregating Results of Multiple Machine Learning Elements, Haifeng Qian, U.S. Patent 11922285, 2024.

Neural Belief Reasoner, Haifeng Qian, China Patent 110414682B, 2023.

Neural Belief Reasoner, Haifeng Qian, U.S. Patent 11630987, 2023.

Facilitating Neural Networks, Haifeng Qian and Mark Wegman, U.S. Patent 11556794, 2023.

L2 Non-expansive Neural Networks, Haifeng Qian and Mark Wegman, U.S. Patent 11521014, 2022.

Clock Network Analysis Using Harmonic Balance, Peter Feldmann and Haifeng Qian, U.S. Patent 10620659, 2020. 

Chip Transient Temperature Predictor, Chen-Yong Cher and Haifeng Qian, U.S. Patent 10528097, 2020. 

Concept Analysis Operations Utilizing Accelerators, Emrah Acar, Rajesh R. Bordawekar, Michele M. Franceschini, Luis A. Lastras-Montano, Ruchir Puri, Haifeng Qian, Livio B. Soares, U.S. Patent 10373057, 2019. 

Ranking Related Objects Using Blink Model Based Relation Strength Determinations, Haifeng Qian, Hui Wan, U.S. Patent 9946800, 2018. 

Control Path Power Adjustment for Chip Design, Christopher J. Berry, Kaustav Guha, Jose L. Neves, Haifeng Qian, Sourav Saha, U.S. Patent 9703910, 2017. 

Matrix Ordering for Cache Efficiency in Performing Large Sparse Matrix Operations, Emrah Acar, Rajesh R. Bordawekar, Michele M. Franceschini, Luis A. Lastras-Montano, Ruchir Puri, Haifeng Qian, Livio B. Soares, U.S. Patent 9606934, 2017. 

Cross-hierarchy Interconnect Adjustment for Power Recovery, Christopher J. Berry, Ricardo H. Nigaglioni, Haifeng Qian, Sourav Saha, U.S. Patent 9552451, 2017. 

Malicious Activity Detection of a Processing Thread, Chen-Yong Cher, Eren Kursun, Haifeng Qian, U.S. Patent 9218488, 2015. 

Malicious Activity Detection of a Functional Unit, Chen-Yong Cher, Eren Kursun, Haifeng Qian, U.S. Patent 9088597, 2015. 

Direct Current Circuit Analysis Based Clock Network Design, Charles J. Alpert, Joseph N. Kozhaya, Zhuo Li, Joseph J. Palumbo, Haifeng Qian, Phillip J. Restle, Chin Ngai Sze, Ying Zhou, U.S. Patent 8775996, 2014. 

Designing a Robust Power Efficient Clock Distribution Network, Charles J. Alpert, Joseph N. Kozhaya, Zhuo Li, Joseph J. Palumbo, Haifeng Qian, Phillip J. Restle, Chin Ngai Sze, Ying Zhou, U.S. Patent 8677305, 2014. 

Converged Large Block and Structured Synthesis for High Performance Microprocessor Designs, Minsik Cho, Victor N. Kravets, Smita Krishnaswamy, Dorothy Kucar, Jagannathan Narasimhan, Ruchir Puri, Haifeng Qian, Haoxing Ren, Chin Ngai Sze, Louise H. Trevillyan, Hua Xiang, Matthew M. Ziegler, U.S. Patent 8271920, 2012. 

Regular Local Clock Buffer Placement and Latch Clustering by Iterative Optimization, Ruchir Puri, Haifeng Qian, Chin Ngai Sze, James Warnock, U.S. Patent 8104014, 2012. 

Simultaneous Power and Timing Optimization in Integrated Circuits by Performing Discrete Actions on Circuit Components, Emrah Acar, Haifeng Qian, U.S. Patent 7689942, 2010.