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I participated in URP (Undergraduate Research Program) and Capstone Design at Sungkyunkwan University as a team leader under the supervision of Professor Kang-Yoon Lee. Our team designed circuits from two papers we read. Below are two circuits we designed.
In-Memory Boolean Computing array
In-Memory Boolean Computing array
Our team designed an In-Memory-Computing (IMC) circuit from the paper we read: X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories.
A. Agrawal et al., TCAS-I, 2018
[Figure 1] X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories
CONV-SRAM
CONV-SRAM
Our team also designed an IMC circuit from the paper we read: CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks, 2019 IEEE Journal of Solid-State Circuits.
A. Biswas et al., JSSC, 2019
[Figure 2] Overall architecture of the CONV-SRAM showing local arrays, column-wise DACs, and row-wise ADCs to implement convolution as weighted averaging.
Digital input voltages are converted into analog RBL voltages by DAC consisting of a digital-to-time Converter (DTC) and time-to-analog Converter (TAC.) Node voltages of 10T-SRAMs decide whether RBL or RBLB will discharge. MAV & ADC operation is achieved by charge-sharing among the local bit-line capacitance.
With this IMC array, our team sought to design an area-efficient Recycling-Layer: A single SRAM array that can conduct multilayer CNN by pre-charging RBL with analog voltage, which is the computation result of the former layer.
[Figure 3] Suggested idea: recycling layer
I considered storing the input layer's result in an additional capacitor, but it kept making some errors. Stored voltage in the additional capacitor can't be delivered to the second layer without loss since there is another charge-sharing between this capacitor and the SRAM array. Also, it was my mistake to forget about using activation functions between the layers, such as an operational amplifier that implements a tanh-like activation function.
Our team participated in ITC-CSCC 2023 (International Technical Conference on Circuits/Systems, Computers and Communications) Undergraduate IC track Poster session: “Computing-In-Memory based on MAV SRAM using Recycling-Layer”. (p59)
[Click here!] to see the ITC-CSCC Program book p59
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