Justin Gottschlich

Senior Staff Research Scientist, Intel Labs

I am a senior staff research scientist at Intel Labs. I perform research in machine learning with a focus on anomaly detection, programming languages, and autonomous systems. I also oversee and guide the research vision of a few different research teams at Intel and academia. If you are a graduate student or professor with similar interests, please contact me at justin.gottschlich@intel.com or justin.gottschlich@gmail.com to discuss collaboration opportunities.

I was previously the director of game engineering at Machine Zone, where I briefly oversaw the engineering effort of MZ's hugely successful games Game of War and Mobile Strike. I also hold an appointment as an adjunct professor at the University of Colorado-Boulder in the department of Electrical, Computer, and Energy Engineering where I run the neural network design course. For over fifteen years, I have run my own software company, Nodeka, LLC., of which I am the founder and CEO.

My CV is here and this is a complete listing of my issued patents (9 issued patents and 23 patent applications as of May, 2017).

RECENT ACTIVITY

2017

Program Chair and Founding Member, First ACM SIGPLAN Workshop on Machine Learning and Programming Languages (MAPL)

Deputy Technical Lead and Founding Member, NSF/Intel Partnership on Computer Assisted Programming for Heterogeneous Architectures

Under review: "BF-Programmer: A Counterintuitive Approach to Autonomously Building Simplistic Programs Using Genetic Algorithms"

Patent issued: "Unbounded transactional memory with forward progress guarantees using a hardware global lock"

Patent issued: "Apparatus and method for improved lock elision techniques"

2016

Talk at Intel's High Performance Developers Conference: "Using Machine Learning To Avoid the Unwanted"

Intel Research Velocity Challenge Winner: "Using Deep Neural Networks to Identify and Fix Performance and Correctness Anomalies in Data Centers"

Patent issued: "Mechanism for facilitating dynamic and efficient management of instruction atomicity violations in software programs at computing systems"

Patent issued: "Transactional memory management techniques"

Patent issued: "Replay execution of instructions in thread chunks in the chunk order recorded during previous execution"

Patent issued: "Methods and systems to identify and reproduce concurrency violations in multi-threaded programs"

2015

General Chair and Steering Committee Member, TRANSACT 2015

Director of Engineering at Machine Zone

Paper at PACT: "TSXProf: Profiling Hardware Transactions"

Patent issued: "Methods and systems to identify and reproduce concurrency violations in multi-threaded programs using expressions"

Patent issued: "Processor with memory race recorder to record thread interleavings in multi-threaded software"

Patent issued: "Methods and apparatus to manage concurrent predicate expressions"

2014

Program Chair, TRANSACT 2014

Paper at PACT: "Invyswell: A Hybrid Transactional Memory for Haswell's Restricted Transactional Memory"

Paper at IWOOMP: "Towards Transactional Memory for OpenMP"

2013

Application Track Chair, TRANSACT 2013

Paper at PACT: "Concurrent Predicates: A Debugging Technique for Every Parallel Programmer"

Paper at HotPar: "Using Elimination and Delegation to Implement a Scalable NUMA-Friendly Stack"

Paper at HotPar: "But How Do We Really Debug Transactional Memory Programs?"

Paper at ISCA: "QuickRec: Prototyping an Intel Architecture Extension for Record and Replay of Multithreaded Programs"

Paper at TRANSACT: "Generic Programming Needs Transactional Memory"

2012

Paper at PACT: "Visualizing Transactional Memory"

Paper at HotPar: "Concurrent Predicates: Finding and Fixing the Root Cause of Concurrency Violations"

2011

Paper at MICRO: "CoreRacer: A Practical Memory Race Recorder for Multicore x86 TSO Processors"

Paper at LCPC: "Optimizing the Concurrent Execution of Locks and Transactions"

2010

Paper at CGO: "An Efficient Software Transactional Memory Using Commit-Time Invalidation" (Best Presentation Award)

2009

Paper at ICOOOLPS: "An Efficient Lock-Aware Transactional Memory Implementation"

2008

Paper at EPHAM: "Extending Contention Managers for User-Defined Priority-Based Transactions"


FORMER STUDENTS

PhD co-advisor: Irina Calciu, Brown University - VMWare

PhD committee member: Wenjia Ruan, Lehigh University - Qualcomm