Senior Staff Research Scientist, Intel Labs
I am a senior staff research scientist at Intel Labs. I perform research in machine learning with a focus on anomaly detection, programming languages, and autonomous systems. I also oversee and guide the research vision of a few different research teams at Intel and academia. If you are a graduate student or professor with similar interests, please contact me at email@example.com or firstname.lastname@example.org to discuss collaboration opportunities.
I was previously the director of game engineering at Machine Zone, where I briefly oversaw the engineering effort of MZ's hugely successful games Game of War and Mobile Strike. I also hold an appointment as an adjunct professor at the University of Colorado-Boulder in the department of Electrical, Computer, and Energy Engineering where I run the neural network design course. For over fifteen years, I have run my own software company, Nodeka, LLC., of which I am the founder and CEO.
Program Chair and Founding Member, First ACM SIGPLAN Workshop on Machine Learning and Programming Languages (MAPL)
Deputy Technical Lead and Founding Member, NSF/Intel Partnership on Computer Assisted Programming for Heterogeneous Architectures
Patent issued: "Apparatus and method for improved lock elision techniques"
Talk at Intel's High Performance Developers Conference: "Using Machine Learning To Avoid the Unwanted"
Intel Research Velocity Challenge Winner: "Using Deep Neural Networks to Identify and Fix Performance and Correctness Anomalies in Data Centers"
Patent issued: "Transactional memory management techniques"
General Chair and Steering Committee Member, TRANSACT 2015
Director of Engineering at Machine Zone
Paper at PACT: "TSXProf: Profiling Hardware Transactions"
Patent issued: "Methods and apparatus to manage concurrent predicate expressions"
Program Chair, TRANSACT 2014
Paper at IWOOMP: "Towards Transactional Memory for OpenMP"
Application Track Chair, TRANSACT 2013
Paper at HotPar: "Using Elimination and Delegation to Implement a Scalable NUMA-Friendly Stack"
Paper at HotPar: "But How Do We Really Debug Transactional Memory Programs?"
Paper at TRANSACT: "Generic Programming Needs Transactional Memory"
Paper at PACT: "Visualizing Transactional Memory"
Paper at LCPC: "Optimizing the Concurrent Execution of Locks and Transactions"
Paper at CGO: "An Efficient Software Transactional Memory Using Commit-Time Invalidation" (Best Presentation Award)
Paper at ICOOOLPS: "An Efficient Lock-Aware Transactional Memory Implementation"
PhD co-advisor: Irina Calciu, Brown University - VMWare
PhD committee member: Wenjia Ruan, Lehigh University - Qualcomm