Justin Gottschlich

Senior Staff Research Scientist, Intel Labs

Artificial Intelligence Lead, Programming Systems Research

Principal Investigator and Co-Founder, Intel / NSF CAPA Research Center

I am a senior staff research scientist at Intel Labs, where I lead the artificial intelligence team in the programming systems research group. I'm also Intel's lead principal investigator and co-founder of the joint Intel/NSF CAPA research center.

I perform research in machine learning with a focus on machine programming, anomaly detection, and autonomous systems. I also oversee and guide the research vision of a few different research teams at Intel, Brown, MIT, Stanford, and UW. I oversee an industrial collaboration between Intel and BMW on anomaly detection for autonomous vehicles. If you are a graduate student or professor with similar interests, please contact me at justin.gottschlich@intel.com or justin.gottschlich@gmail.com to discuss collaboration opportunities.

I was previously the director of engineering at Machine Zone, where I oversaw the engineering of Game of War and Mobile Strike. I am an adjunct professor at the University of Colorado-Boulder where I occasionally run a neural network design course. For twenty years, I have run my own software company, Nodeka, LLC., of which I am the founder and CEO.

My (somewhat dated) CV is here and this is a complete listing of my issued patents (16 issued patents with over 40 pending as of June 2018).



MAPL presentation: "The Three Pillars of Machine Programming" (joint with MIT)

Patent issued: "Transactional memory management techniques"

Program committee member, SysML 2019.

Invited talk at VMware Research: "Anomaly Detection for Practical Systems (and a Tiny Bit of Machine Programming)"

Patent issued: "Enabling maximum concurrency in a hybrid transactional memory system"

Patent issued: "Processor with transactional capability and logging circuitry to report transactional operations"

MAPL paper: "The Three Pillars of Machine Programming" (joint with MIT)

GRASP / PRECISE Industry Symposium at University of Pennsylvania: "Deep Learning for Autonomous Driving" (slides forthcoming)

Special seminar at University of Pennsylvania: "The Future of Anomaly Detection" (slides forthcoming)

SysML paper: "Precision and Recall for Range-Based Anomaly Detection" (joint with Brown and Microsoft)

SysML paper: "Greenhouse: A Zero-Positive Machine Learning System for Time-Series Anomaly Detection" (joint with Brown and Microsoft)

SysML paper: "Toward Scalable Verification for Safety-Critical Deep Networks" (joint with Stanford)

Patent issued: "Shared Memory Interleavings for Instruction Atomicity Violations"

Patent issued: "Technologies for root cause identification of use-after-free memory corruption bugs"

General Chair, Second ACM SIGPLAN Workshop on Machine Learning and Programming Languages (MAPL)


Intel's Principal Investigator for the joint Intel/NSF CAPA research center.

Patent issued: "Methods and apparatus to manage concurrent predicate expressions"

Under review: "AutoCon: Regression Testing for Detecting Cache Contention Anomalies Using Autoencoder"

Under review: "AI Programmer: Autonomously Creating Software Programs Using Genetic Algorithms"

Patent issued: "Software replayer for transactional memory programs"

White Paper: "Using Machine Learning to Solve the Ninja Gap"

Program Chair and Founding Member, First ACM SIGPLAN Workshop on Machine Learning and Programming Languages (MAPL)

Deputy Technical Lead and Founding Member, NSF/Intel Partnership on Computer Assisted Programming for Heterogeneous Architectures

Patent issued: "Unbounded transactional memory with forward progress guarantees using a hardware global lock"

Patent issued: "Apparatus and method for improved lock elision techniques"


Talk at Intel's High Performance Developers Conference: "Using Machine Learning To Avoid the Unwanted"

Intel Research Velocity Challenge Winner: "Using Deep Neural Networks to Identify and Fix Performance and Correctness Anomalies in Data Centers"

Patent issued: "Mechanism for facilitating dynamic and efficient management of instruction atomicity violations in software programs at computing systems"

Patent issued: "Transactional memory management techniques"

Patent issued: "Replay execution of instructions in thread chunks in the chunk order recorded during previous execution"

Patent issued: "Methods and systems to identify and reproduce concurrency violations in multi-threaded programs"


General Chair and Steering Committee Member, TRANSACT 2015

Director of Engineering at Machine Zone

Paper at PACT: "TSXProf: Profiling Hardware Transactions"

Patent issued: "Methods and systems to identify and reproduce concurrency violations in multi-threaded programs using expressions"

Patent issued: "Processor with memory race recorder to record thread interleavings in multi-threaded software"

Patent issued: "Methods and apparatus to manage concurrent predicate expressions"


Program Chair, TRANSACT 2014

Paper at PACT: "Invyswell: A Hybrid Transactional Memory for Haswell's Restricted Transactional Memory"

Paper at IWOOMP: "Towards Transactional Memory for OpenMP"


Application Track Chair, TRANSACT 2013

Paper at PACT: "Concurrent Predicates: A Debugging Technique for Every Parallel Programmer"

Paper at HotPar: "Using Elimination and Delegation to Implement a Scalable NUMA-Friendly Stack"

Paper at HotPar: "But How Do We Really Debug Transactional Memory Programs?"

Paper at ISCA: "QuickRec: Prototyping an Intel Architecture Extension for Record and Replay of Multithreaded Programs"

Paper at TRANSACT: "Generic Programming Needs Transactional Memory"


Paper at PACT: "Visualizing Transactional Memory"

Paper at HotPar: "Concurrent Predicates: Finding and Fixing the Root Cause of Concurrency Violations"


Paper at MICRO: "CoreRacer: A Practical Memory Race Recorder for Multicore x86 TSO Processors"

Paper at LCPC: "Optimizing the Concurrent Execution of Locks and Transactions"


Paper at CGO: "An Efficient Software Transactional Memory Using Commit-Time Invalidation" (Best Presentation Award)


Paper at ICOOOLPS: "An Efficient Lock-Aware Transactional Memory Implementation"


Paper at EPHAM: "Extending Contention Managers for User-Defined Priority-Based Transactions"


PhD co-advisor: Irina Calciu, Brown University - VMWare

PhD committee member: Wenjia Ruan, Lehigh University - Qualcomm

PhD committee member: Mohammad Mejbah ul Alam - Intel Labs