GIST Integrated Circuit Design Lab

International

2024

• Il-Min Yi, Srujan Kumar Kaile, Yuanming Zhu, Julian Camilo Gomez Diaz, Sebastian Hoyos, and Samuel Palermo, “A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET,” IEEE J. Solid-State Circuits (JSSC), 2024.  [Link]

2023

• Po-Hsuan Chang, Anirban Samanta, Peng Yan, Mingye Fu, Mehmet Berkay On, Ankur Kumar, Hyungryul Kang, Il-Min Yi, Dedeepya Annabattuni, David Scott, Robert Patti, Yang-Hang Fan, Yuanming Zhu, Samuel Palermo, and S. J. Ben Yoo, "A 3D Integrated Energy-Efficient Transceiver Realized by Direct Bond Interconnect of Co-Designed 12 nm FinFET and Silicon Photonic Integrated Circuits,” Journal of Lightwave Technology, July 2023. [Link]

• Peng Yan, Po-Hsuan Chang, Anirban Samanta, Mingye Fu, Yu Zhang, Mehmet Berkay On, Ankur Kumar, Hyungryul Kang, Il-Min Yi, Dedeepya Annabattuni, David Scott, Robert Patti, Yang-Hang Fan ,Yuanming Zhu, S. J. Ben Yoo, and  Samuel Palermo, “A 25-Gb/s 3-D Direct Bond Silicon Photonic Receiver in 12-nm FinFET,” IEEE Solid-State Circuits Letters (SSCL), July 2023. [Link]

• Il-Min Yi, Srujan Kumar Kaile, Yuanming Zhu, Julian Camilo Gomez Diaz, Sebastian Hoyos, and Samuel Palermo, “A 50Gb/s DAC-Based Multicarrier Polar Transmitter in 22nm FinFET,” IEEE Symposium on VLSI Circuits (VLSI), June 2023. [Link]

• Po-Hsuan Chang, Anirban Samanta, Peng Yan, Mingye Fu, Yu Zhang, Mehmet Berkay On, Ankur Kumar, Hyungryul Kang, Il-Min Yi, D. Annabattuni, David Scott, Robert Patti, Yang-Hang Fan, Yuanming Zhu, S. J. Ben Yoo, and  Samuel Palermo, “A Sub-500fJ/bit 3D Direct Bond Silicon Photonic Transceiver in 12nm FinFET,” IEEE Symposium on VLSI Circuits (VLSI), June 2023. [Link]

• Yuanming Zhu, Tong Liu, Srujan Kumar Kaile, Shiva Kiran, Il-Min Yi, Ruida Liu, Julian Camilo Gomez Diaz, Sebastian Hoyos, and Samuel Palermo, “A 38-GS/s 7-bit Pipelined-SAR ADC With Speed-Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET,” IEEE J. Solid-State Circuits (JSSC), Aug. 2023. [Link]

• Hyungryul Kang, Inhyun Kim, Ruida Liu, Ankur Kumar, Il-Min Yi, Yuan Yuan, Zhilhong Huang, and Samuel Palermo, “A 42.7Gb/s Optical Receiver with Digital CDR in 28nm CMOS,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2023.

• Anirban Samanta, Po-Hsuan Chang, Peng Yan, Mingye Fu, Mehmet Berkay On, Ankur Kumar, Hyungryul Kang, Il-Min Yi, Dedeepya Annabattuni, Yu Zhang, David Scott, Robert Patti, Yang-Hang Fan, Yuanming Zhu, Samuel Palermo, and S. J. Ben Yoo, "A Direct Bond Interconnect 3D Co-Integrated Silicon-Photonic Transceiver in 12nm FinFET With -20.3dBm OMA Sensitivity and 691fJ/bit,” Optica Optical Fiber Communication Conference (OFC), Mar. 2023.

• Yuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, Il-Min Yi, Tong Liu, Sebastian Hoyos, and Samuel Palermo, “A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET,” IEEE J. Solid-State Circuits (JSSC), 2023. [Link]

2022

• Yuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, Il-Min Yi, Tong Liu, Sebastian Hoyos, and Samuel Palermo, “A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET,” IEEE Custom Integrated Circuits Conference (CICC), 2022. [Link]

• Yuanming Zhu, Tong Liu, Srujan Kumar Kaile, Julian Camilo Gomez Diaz, Shiva Kiran, Il-Min Yi, Ruida Liu, Sebastian Hoyos, and Samuel Palermo, “A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET,” IEEE Custom Integrated Circuits Conference (CICC), 2022. [Link]

• Marjan Fariborz, Mahyar Samani, Pouya Fotouhi, Roberto Proietti, Il-Min Yi, Venkatesh Akella, Jason Lowe-Power, Samuel Palermo, and S. J. Ben Yoo, “LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads,” International Supercomputing Conference (ISC) High Performance, 2022. [Link]

2021

• Il-Min Yi, Naoki Miura, and Hideyuki Nosaka, “A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS,” IEEE J. Solid-State Circuits (JSSC), Feb. 2021. [Link]

• Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, and Hideyuki Nosaka, “A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8x Time-Domain Latch Interpolation,” IEEE J. Solid-State Circuits (JSSC), Feb. 2021. [Link]

2019

• Siyoung Lee, Junsoo Kim, Inyeol Yun, Geun Yeol Bae, Daegun Kim, Sangik Park, Il-Min Yi, Wonkyu Moon, Yoonyoung Chung, and Kilwon Cho, “An Ultrathin Conformable Vibration-Responsive Electronic Skin for Quantitative Vocal Recognition,” Nature Communications, 2019. [Link]

2018

• Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, and Hideyuki Nosaka, “A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8x Time-Domain Interpolation,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2018. [Link]

• Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, and Hideyuki Nosaka, “A Summer-Embedded Sense Amplifier for High-Speed Decision Feedback Equalizer,” IEICE Transactions of Fundamentals of Electronics, Communications and Computer Sciences, Nov. 2018. [Link]

• Il-Min Yi, Min-Kyun Chae, Seok-Hun Hyun, Seung-Jun Bae, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park, “A time-based receiver with 2-tap decision feedback equalizer for single-ended mobile DRAM interface,” IEEE J. Solid-State Circuits (JSSC), Jan. 2018. [Link]

2017

• Il-Min Yi, Min-Kyun Chae, Seok-Hun Hyun, Seung-Jun Bae, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park, “A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2017. [Link]

2016

• Soo-Min Lee, Ji-Hoon Lim, Il-Min Yi, Young-Jae Jang, Hae-Kang Jung, Kyunghoon Kim, Daehan Kwon, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park, “A Single-Ended Parallel Transceiver with Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface,” IEEE J. Solid-State Circuits (JSSC), 2016. [Link]

• Il-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Young-Jae Jang, Young-Chul Cho, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park, “A Low-EMI Four-Bit Four-Wire Single-Ended DRAM Interface by Using a Three-Level Balanced Coding Scheme,” IEEE Symposium on VLSI Circuits (VLSI), June 2016. [Link]

• Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park, “A 40 mV-Differential-Channel-Swing Transceiver using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer with a CML driver at 9 Gb/s,” IEEE Trans. Circuits Syst. I (TCS-I), Jan. 2016. [Link]

2015

• Young-Jae Jang, Il-Min Yi, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park, "EMI Issues in Pseudo-Differential Signaling for SDRAM Interface," J. Semicond. Technol. Sci. (JSTS), Oct. 2015. [Link]

2014

• Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park, “A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination,” IEEE Trans. Circuits Syst. II (TCS-II), Dec. 2014. [Link]

• Soo-Min Lee, Il-Min Yi, Hae-Kang Jung, Hyunbae Lee, Yong-Ju Kim, Yun-Saing Kim, Byungsub Kim, Jae-Yoon Sim, and Hong-June Park, “An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface,” IEEE J. Solid-State Circuits (JSSC), Nov. 2014. [Link]

2012

• Il-Min Yi, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, and Hong-June Park, “An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits,” Proc. International SoC Design Conference (ISoCC), 2012. [Link]

• Hae-Kang Jung, Il-Min Yi, Soo-Min Lee, Jae-Yoon Sim, and Hong-June Park, “A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines,” IEEE J. Solid-State Circuits (JSSC), Sep. 2012. [Link]

Domestic

2014

• 수신 단 TIA 터미네이션 기법의 단일 신호선 듀오바이너리 송수신 단 회로, 이수민, 이일민, 김병섭, 심재윤, 박홍준, 대한전자공학회 SoC 학술대회, 2014

2009

• SIGMA-SPICE: A Parallel Mode SPICE for Multi-core CPU, 이일민, 심재윤, 박홍준, 대한전자공학회 학술심포지움, 2009

• SIGMA-SPICE: A SPICE3-based mixed-mode and parallel Monte Carlo circuit simulator, 엄지용, 이일민, 심재윤, 박홍준, 대한전자공학회 SoC 학술대회, 2009