The Schedule

1:30 - 1:35 pm

Welcome 

1:35 - 2:00 pm

FPGA Architecture with a DL Lens

2:05 - 2:35 pm

FPGA DL accelerators and architectures

Break 2:35 pm - 2:40 pm

2:40 - 3:10 pm

Modifications to the Traditional FPGA Blocks

3:10 - 4:20 pm

New DL-Optimized FPGA Blocks

Break 4:20 pm - 4:25 pm

4:25 - 5:30 pm

Panel discussion