Future Research plans

Moore's law has been the driver in semiconductor technology, describing the advancement of technological capability since its introduction in 1965. Progress in the field of the nano-scale device resulted in billions of transistors inside a modern-day VLSI chip with almost no room for further miniaturization leading to an eventual slowing down of Moore's law. The slowing down of Moore's law is not just hype but a reality that requires serious attention. More and more transistors are squeezed inside a chip, and consequently, there is not much room left at the bottom anymore. Moreover, the memory bottleneck problem in the traditional von-Neumann architecture urges researchers to find an alternative architecture that rectifies this problem. DRAM, SRAM, and Flash are traditional memory technologies rapidly reaching their size and power consumption limits. In addition, due to its restricted endurance, the Flash memory cannot be scaled beyond the current regime. All of these contribute to the quest for emerging technologies to solve the above problem.

Memristors, an emerging device, also classifiable as Resistive RAM (RRAM), have the potential to answer these problems. A memristor is a two-terminal passive device capable of remembering the charge that previously flowed through it. Memristor, a concatenation of memory and resistor, was known to be fabricated successfully only in 2008 by HP Labs. Memristors exhibit unique properties that support various logic and memory operations. Due to the advancement in memristor-based research, they are expected to replace flash memory devices shortly. The unique properties of memristor lay the foundation for an architecture beyond the traditional von-Neumann architecture, commonly known as in-memory computing architecture (IMC). In IMC, both data processing and storage can be performed in the same memory unit without having a separate processor and memory. Memristors can be efficiently fabricated as a crossbar array. Diverse memristor-based logic designs have been reported, such as MAGIC, IMPLY-based, BDD-based, AIG-based, and MIG-based, which can be carried out on the crossbar. The lack of mitigation for the sneak-path issue in the memory array is a typical flaw in these systems, resulting in erroneous data processing. 

Memristor, a two-terminal passive circuit element, also known as Resistive Random Access Memory, is a hot topic in the research community to enhance the existing knowledge in the non-von Neumann computing architecture. Due to its unique properties, it can be efficiently integrated into various applications, particularly neuromorphic computing architecture, where memristors are used as synapses/synaptic weights. 

My research plans for the foreseeable future are briefly highlighted below:

1. Extensive research on the existing integration of in-memory computing architecture: The need for a non-von Neumann computing architecture has increased significantly over the last few years to tackle the apparent memory-wall problem. Memristor is an excellent candidate to build an in-memory computing architecture. Research on the device and architectural levels is a must to enhance the current knowledge of next-generation computing architecture. 

2. Explore a better logic synthesis technique and algorithms for memristor-based in-memory computing architecture. Logic synthesis is an integral part of non-von Neumann computing architecture as data processing, evaluated directly in the memory array, relies on the computational method. Hence, it is essential to find an efficient logic synthesis technique for this architecture. The logic synthesis also involves data structure that optimizes the circuit using some scheduling or optimization algorithms. Efficient algorithms and architectural design are essential aspects of logic synthesis.

3. Extensive research on the existing neuromorphic computing architecture: an architecture that mimics the biological neural network in the form of the artificial neural network is also known as neuromorphic computing architecture. Due to its unique properties, the memristor is a suitable candidate to portray the neurons in the human brain. As AI is the way forward, enhancing the development of it using memristor as the basis is also the way forward.

4. Design a scalable architecture for vector-matrix multiplication, which is the foundation of neuromorphic operations. The main aim is to integrate memristor crossbar architecture (2-dimensional and 3-dimensional) for efficient MVM operations.

5. Extensive research and formulation of an efficient single-layered or multi-layered memristor crossbar-based neural network. Various findings on neuromorphic computing architecture are limited to 2-dimensional arrays apart from the few that reported a 3-dimensional array. Further development of a 3-dimensional memory array is essential to achieve higher performance and better area usage.

6. Design architecture and algorithms for neuromorphic computing applications. Designing an efficient and scalable neuromorphic computing architecture requires efficient algorithmic and architectural design. 

7. Developing energy-efficient algorithms for deep learning applications. High power consumption is the current hurdle in deep learning architecture. It is worthwhile to try to reduce the energy by designing efficient algorithms.

8. Collaboration of multidisciplinary research areas is required to turn existing research into reality. This is one crucial plan for research in neuromorphic computing architecture. Device fabrication and production for commercial usability involve the collaboration of multidisciplinary research areas from computer science and electronics. It is a must to collaborate to achieve these proposals.

9. Explore a better logic synthesis technique and algorithms for memristor-based in-memory computing architecture. Logic synthesis is an integral part of non-von Neumann computing architecture as data processing, evaluated directly in the memory array, relies on the computational method. Hence, it is essential to find an efficient logic synthesis technique for this architecture.