Co-located with FCCM on May 13, 2026, from 9AM to 12PM, in Atlanta, GA.
Room: 114 (near the registration table) in Georgia Tech CODA Building
Organizers: Kazutomo Yoshii (Argonne), Tao Wei, Jon Calhoun (Clemson University), Peipei Zhou (Brown University)
Visit the FCCM schedule page
The CASI workshop focuses on custom and programmable architectures for scientific instruments, with an emphasis on real-time processing of high-rate sensor data such as X-ray detectors. As detector data rates outpace general-purpose systems, the workshop highlights FPGA- and ASIC-based solutions for low-latency streaming data processing, including hardware/software co-design, near-sensor and on-chip programmable architectures, and open-source hardware frameworks.
The workshop is intended for computer architects, FPGA/ASIC designers, and researchers developing scientific instruments and experimental facilities. It will feature 8 lightning talks (15-minute talk and 5-minute Q&A) and aims to foster collaboration in domain-specific architectures, real-time data processing, and rapid hardware prototyping.
[Agenda]
9:00 Opening (Kazutomo Yoshii, Argonne)
9:10 Microsecond-latency Customized Accelerator for Real-time Models (Peipei Zhou, Brown University; Shixin Ji, Brown University)
Speaker Bio: Peipei Zhou is an Assistant Professor at Brown University, and her research interests are hardware/software co-design for customized computing. Shixin Ji is a 3rd-year Ph.D. student under the supervision of Prof. Peipei Zhou at Brown University. His research interests lie in customizing deep learning accelerators for autonomous systems and scientific research.
9:30 FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration (Xingzhen Chen, Brown University)
Speaker Bio: Xingzhen Chen is a 3rd-year Ph.D. student under the supervision of Prof. Peipei Zhou at Brown University. His research interests lie in hardware accelerators and real-time systems.
9:50 Aggregated I/O Strategies for Asynchronous Checkpoint-Restart of LLMs and Scientific Simulations (Mikaila Gossman, Clemson University)
Speaker Bio: Mikaila Gossman is a Ph.D. candidate under the supervision of Dr. Jon Calhoun. Her research interests are in mitigating large-scale I/O bottlenecks for asynchronous checkpoint-restart on HPC systems.
10:10 Securing Lossy Compressed Data (Ruiwen Shan, Clemson University)
Speaker Bio: Ruiwen is a Ph.D. candidate under the supervision of Dr. Jon Calhoun. Her research focuses on the interplay of data security and lossy compression on HPC and edge systems.
10:30 Accelerating Lossy Compression Ratio Prediction for Scientific Data (Jon Calhoun, Clemson University)
Bio: Jon Calhoun is an Associate Professor at Clemson University, where his research focuses on lossy compression, parallel I/O, and application-based fault tolerance.
10:50 An End-to-End Efficient Dataflow Framework for DiT-Based Models (Yazhe Zhang, Clemson University)
Speaker Bio: Yazhe Zhang is a 3rd-year Ph.D. student under the supervision of Prof. Tao Wei at Clemson University. Her research interests lie in hardware accelerators and dataflow design.
11:10 Assessing a RISC-V Accelerator for Cross-Section Lookup in Chipyard (Andrew Ledbetter, Clemson University)
Speaker Bio: Andrew Ledbetter is an incoming Master’s student in Computer Engineering at Clemson University. His research focuses on HW/SW co-design for nuclear HPC applications.
11:30 AI-Assisted Hardware Design and Verification: A Feasibility Study (Connor Bohannon, Argonne)
Speaker Bio: Connor Bohannon is a Computer Architecture Researcher at Argonne National Laboratory. His research interests include digital circuit design and verification, AI-assisted hardware design, FPGA-based accelerator development, and open-source hardware workflows for scientific computing.
11:50 Wrap-up