Emerging HPC and datacenter applications, in domains such artificial intelligence (AI), data analytics, scientific computing, enterprise computing etc., are experiencing a rapid growth regarding the amount of data to be processed combined with algorithm complexity. As a promising solution, industry and academia are moving toward more and more heterogeneous architectures based on various accelerators in many different parts of hardware infrastructures. Might this be an opportunity for the FPGAs to find a new path to provide a significantly better performance per watt than other solutions?

One of the main goals of this workshop is to better understand present, and future challenges for FPGA devices, and at the same time create awareness and engagement around some of the initiatives led by professionals from the academia and the industry. That will allow collaborative activities between academia and the industry, and the creation of placeholders for ongoing international research projects and follow-up their evolution along the timesharing knowledge. 

The workshop will include technical presentations to develop a complete view of the ecosystem, from software to hardware, and build on top of it the next generation of HPC/datacenter systems.

Motivation

• More heterogeneity is required, furthering the current strong focus on DPUs, GPUs (mainstream) and application specific accelerators such as TPUs, etc.

• Proven chiplets/2.5D/3D packaging technologies open the door to more flexible FPGA integration into mainstream SoCs and super-chips. 

• Although ASICs are most efficient, they are not inline with emerging fast-pacing algorithmic innovations.

• Environmental awareness is a hot topic, might FPGAs be an alternative for more green computing?

Scope and objectives

The purpose of this workshop is to provide an overview of the advancements and challenges in the HPC and datacenter domains by using FPGAs, considering the academia and industry considerations and points of view. As part of this, and due to the inherent complexity for managing these devices reducing their accessibility significantly compared to other kinds of accelerators, this workshop aims to tackle the surrounding environment needs to reverse, or at least alleviate this situation.

This workshop offers a forum for researchers and developers to discuss how all the different pieces of the ecosystem impacts on spreading and popularizing the use of the FPGAs as solutions for traditional and emerging HPC and datacenter applications, including applications, programming models, and toolchains among others.

Topics of Interest

The topics of interest for this workshop includes, but it is not constrained to the following:

• Advances and future trends and challenges in FPGA for HPC and datacenter systems

• Novel methods, tools, and programming models to enhance FPGAs’ functionalities across HPC and datacenter systems

• FPGA architecture design flow for HPC and datacenter

• Programming environments for reconfigurable systems to increase the rate of productivity

• Reconfigurable computing applications and/or efficient algorithms for reconfigurable hardware

• Other topics related to FPGAs, reconfigurable computing and HPC

Program

10:00 - 10:15 Workshop opening (workshop co-chairs)

10:15 – 11:00 Panel session - Academia focused (chair: Holger Fröning (Heidelberg University))

Panelists: John Davis (BSC), Babak Falsafi (EPFL), Dirk Koch (Heidelberg University), Cathal McCabe (AMD/XILINX), Michael Lass (Paderborn University)

11:00 – 11:30 Coffee break 

11:30 - 13:00 Tech session 1: FPGA Technology (chair: Teresa Cervero (BSC))

• Dirk Koch (Heidelberg University): Resource-Elastic Dynamic Stream Processing on FPGAs for Database Acceleration and Data Analytics [slides]
  Abstract: This talk will show how pipelines built of composable operator modules can be stitched together using partial reconfiguration on FPGAs. For database acceleatrion and data analytics applications, this allows it to build optimized accelerator pipelines for problems that are only known at runtime. Moreover, the approach allows us to maximize the amount of work performed per unit I/O for improved performance and energy efficiency. The presented system provides a full ecosystem comprising supporting IP, compile scripts for implementing stichable accelerator modules, a bitstream manipulation tool to relocate modules, and a runtime system. The latter can compile user requests into operator modules, orchestrate the configuration and initialization of modules, and drives the execution of the hardware. In this presented system, partial FPGA configuration is inferred transparently for the user just by requesting some SQL queries.
  Bio: Dirk Koch is with Heidelberg University Germany and the University of Manchester. His main research interests include run-time reconfigurable systems based on FPGAs, embedded systems, computer architecture, VLSI and hardware security. Dirk’s group developed techniques and the GoAhead tool for implementing self-adaptive distributed embedded control systems based on FPGAs. Current research projects include database acceleration using FPGAs-based stream processing, HPC, and using FPGAs in datacenters. Moreover, his groups maintain the FABulous open-source embedded FPGA generation framework, which was used to design several FPGA chips. Dirk Koch is the author of the book “Partial Reconfiguration on FPGAs” and a co-editor of the book “FPGAs for Software Programmers”.

• Lucian Petrica (AMD): A Vitis-compatible, Modular Communication Stack for Network Attached Accelerators [slides]
  Abstract: As FPGAs gain popularity in the datacenter, we need tools to support rapid development of low latency and high-throughput multi-FPGA applications. A key advantage of FPGA accelerators is their ability to directly connect to the network, without NIC intermediation. We present an open-source communication stack which allows users to easily leverage this unique FPGA capability to partition their Vitis applications across two or more FPGAs. Our stack enables user applications to execute MPI-like communication patterns with minimal host involvement, and full offload for reductions and compression.
  Bio: Lucian Petrica is a senior researcher in the AMD AECG Research Labs in Dublin, Ireland. He received a PhD in computer engineering from the Politehnica University of Bucharest and has had research roles at TU Delft, Ixia, Xilinx, and now AMD. His research interests center on FPGA technology and applications, more specifically dataflow DNN acceleration and distributed FPGA computation. He has been involved in the FINN dataflow inference accelerator compiler, and is now a lead developer for ACCL, a MPI-like collective communication library for datacenter FPGAs.

• Christian Faerber (Intel): Intel FPGAs for HPC and Datacenters [slides]
  Bio: Christian Färber is TS-FAE for FPGA compute acceleration at Intel PSG since 2019 and is working with FPGAs since 2008. He started his career as an hardware development engineer in the automotive industry at Vector Informatik and moved on as senior fellow at CERN in Geneva Switzerland, where he investigated the usage of FPGA compute acceleration in high energy physics for 3 years. Before joining Intel he worked at Thales as senior FPGA design engineer developing railway safety systems. Christian received his diploma in physics from Heidelberg University, and holds a PhD in particle physics from Heidelberg University about radiation effects on SRAM-based FPGA hardware and its mitigation.

• Yoan Dupret (Menta): embedded FPGA IP – acceleration in a pocket [slides]
  Abstract: The presentation is intended to all architects and engineers who are looking at bringing added values with a flexible and highly parallel accelerator inside their chips. First, we will explain what an eFPGA IP is, specifically in comparison to a chips FPGA and with some details on Menta value proposition. As a second part, we will go through some applications of the eFPGA IPs in HPC, datacenters but also for edge computing (e.g. telecommunication, mobility).
  Bio: Since 2016, Yoan Dupret is the Managing Director and CTO of Menta, the leader in embedded FPGA IP cores for chips and smart sensors. Prior to his position at Menta, he held various managerial and technical positions at DelfMEMS, Samsung, CSR, Infineon and Altis Semiconductor. Yoan holds a PhD from CentraleSupelec (France) and an Engineering degree (MSEE) from ESEO (France).

13:00 – 14:00 Lunch

14:00 – 14:45 Keynote (chair: Min Li (Huawei))

• Babak Falsafi (EPFL): Post-Moore Server Architecture [slides]
  Bio: Babak is a Professor in the School of Computer and Communication Sciences and the founder of EcoCloud, an industrial/academic consortium at EPFL investigating sustainable cloud infrastructure. He has made numerous contributions to server design and evaluation. His latest work on workload-optimized server processors laid the foundation for the first generation of Cavium ARM server CPUs, ThunderX. He is a recipient of an Alfred P. Sloan Research Fellowship, and a Fellow of ACM and IEEE.

14:45 - 15:30 Tech session 2: Infrastructure/Applications (chair: Teresa Cervero (BSC))

• John Davis (BSC): Seeing the Future with FPGAs [slides]
  Bio: Dr. John D. Davis is the Director of the Laboratory for Open Computer Architecture at Barcelona Supercomputing Center. He has published over 30 refereed conference and journal papers in Computer Architecture (ASIC and FPGA-based domain-specific accelerators, non-volatile memories and processor design), Distributed Systems, and Bioinformatics. He also holds over 35 issued or pending patents in the USA and Europe. He has designed and built distributed storage systems in research and as products. John has led the entire product strategy, roadmap, and execution for a big data and analytics company. He has worked in research at Microsoft Research, where he also co-advised 4 PhDs, as well as large and small start-up companies. John holds a B.S. in Computer Science and Engineering from the University of Washington. He also holds a M.S. and Ph.D. in Electrical Engineering from Stanford University. At BSC, John is leading the MEEP project and is the technical leader of the eProcesor project and the European PILOT project. He also leads several industrial research collaborations, all centered around a full open source ecosystem from software down to hardware, open source processors and accelerators. John is the founder and chair of the RISC-V Special Interest Group on High Performance Computing (SIG-HPC).

• Michael Lass (Paderborn University): Running 80 FPGAs from two vendors in an HPC cluster - Experiences from the Noctua project at PC2 [slides]
  Bio: Michael Lass received his PhD from Paderborn University in 2022. In his dissertation, he dealt with the acceleration of a quantum chemistry code using accelerator devices, including FPGAs, by exploiting algorithmic approximations and low-precision arithmetic. Since then, he works as a scientific advisor at the Paderborn Center for Parallel Computing (PC2), further developing the FPGA infrastructure and assisting users in the adoption of FPGAs in their own HPC codes.

15:30 - 16:00 Coffee break 

16:00 - 16:45 Tech session 3: Infrastructure/Applications (chair: Federico Iori (BSC))

• Jonas Dann (SAP): Accelerating Modern Databases with FPGAs in the Datacenter [slides]
  Bio: Jonas Dann is a 4th year PhD student at SAP and Heidelberg University. He works on accelerating query processing for non-relational databases such as graph and document databases through analyzing and optimizing memory access patterns. His recent work focuses on the GraphScale architecture which is a scalable graph query processor based on reconfigurable logic.

• Javier Picorel (Huawei): Hardware Accelerators in the Cloud: Opportunities & Challenges [slides]
  Bio: Javier Picorel is a chief architect leading the Intelligent Cloud Infrastructure Research Group in Huawei’s Munich Research Center. The team focuses on shaping and roadmapping the business layout and technology scope of Huawei Cloud via the incubation and prototyping of cutting-edge cloud technologies. He is broadly interested in TCO-efficient cloud infrastructures through the vertical integration of hardware and software in the end of semiconductor technology scaling and skyrocketing popularity of online services. He received a PhD in computer science from EPFL in 2017 and is also the recipient of several awards in Huawei.

16:45 – 17:30 Panel session - Industry focused (chair: Min Li (Huawei))

Panelists: Yoan Dupret (Menta), Christian Faerber (Intel), Lucian Petrica (AMD/XILINX), Javier Picorel (Huawei)

Target audience

The targeted audience is anyone interested in the current efforts carried out world-wide on the reconfigurable computing and heterogeneous solutions in the context of High-Performance and/or datacenter. More particularly, this workshop is of interest to HPC, cloud, edge and datacenter communities, with software and/or hardware background.

Organization

• Teresa Cervero (BSC) - teresa.cervero(at)bsc.es

• Holger Froening (U. Heidelberg) - holger.froening(at)ziti.uni-heidelberg.de

• Min Li (Huawei Research Europe) - minli2(at)huawei.com