Current projects

Neuromorphic Architecture

Neuromorphic architectures require large number of neurons on a chip which necessitates a high performance interconnection network to cope with the large scale communications.




Traffic-Aware On-Chip Networks

Network on Chips provides a scalable and high performance communication paradigm for modern computers including neuromorphic architectures. However, 3D on-chip networks require high cost and unreliable TSVs for their vertical links. In order to improve this challenge, number of vertical links is reduced, which results in irregular Partially Vertical Connected 3D-NoCs, in which unlike the traditional regular mesh topology, the existence of vertical links is incomplete. Therefore, network routers have to share vertical links with an implemented vertical link selection policy. Inappropriate sharing policy of vertical links results in an uneven traffic and performance loss. As a result, this project targets traffic distribution of irregular 3D-NoCs concerning vertical link selection in packet routing process.


Past projects

Fault Tolerant On-Chip Networks


Thermal Aware Chips