Publications

M. Yun, S. Sin, T. Lee, S. M. Yu, J. U. Bae, S. Oh*, "Sub-Coercive Switching in P(VDF-TrFE) Ferroelectric Synapses for Spiking Neural Networks at the Edge" (submitted)

S. H. Kim, S. Sin, J. Kim, J. S. Park, J. H. Lim, S. Oh*, "Stochastic Conduction Pathways in Wide Oxide TFTs Revealed by Transconductance Signature Profiling" (submitted)

J. Park, J. H. Lee, K. Kim, J. Jang, J. H. Baeck, B. Ahn, J. U. Bae, W. Shin*, S. Oh*, "Breaking Temporal Barriers in Trap Emission Characterization of Oxide Semiconductor Transistors by Multi-Timescale Recovery Spectroscopy," (Under Revision)

J. H. Lee, J. Park, P. Vincent, D. Jin, H. Cho, S. Oh, and S. Oh*, "Neural Compact Modeling for Circuit-Aware Optimization of Gate-All-Around FET Parameters,"  IEEE J. Electron Devices Soc. (Under Revision)

S. Sin, S. Oh*, "Deterministic Precessional MRAM with Low Write Error Rate: Fokker-Planck Modeling and Design Optimization,"  IEEE J. Electron Devices Soc.(Under Revision)

S. Kang, J. Kim, S.-M. Lee, S. Baek, S. Oh, Y. Lee, S. Lee, "Steep-Switching Memory FET for Noise-Resistant Reservoir Computing System," Adv. Funct. Mater. e11704, Aug 27, 2025. doi.org/10.1002/adfm.202511704

S. Kim, S. H. Kim, H. U. Hwang, J. Kim, J. W. Kim, I. C. Kwak, B. Kang, S. Lee, S. B. Jo, D. Y. Ryu, H. Kim, J.-M. Myoung, M. S. Kang*, S. Oh*, J. H. Cho*, "Revisiting the role of oxidation in stable and high-performance lead-free perovskite-IGZO junction field-effect transistors," Nat. Comm. 16, 7427, Aug. 11, 2025. doi.org/10.1038/s41467-025-62770-2

H. Ahn, Y. Kim, S. Seo, J. Lee, S. Lee, S. Oh, B. Kim, J. Park, S. Kang, Y. Kim, A. Ham, J. Lee, D. Park, S. Kwon, D. Lee, J.-E. Ryu, J.-C. Shin, A. Sahasrabudhe, K. S. Kim, S.-H. Bae, K. Kang, J. Kim, S. Oh*, and J.-H. Park*, "Artificial optoelectronic synapse featuring bidirectional post-synaptic current for compact and energy-efficient neural hardware," Adv. Mater. 37(34), 2418582, Aug. 28, 2025. doi.org/10.1002/adma.202418582 

J. Park, S. M. Yu, K. Kim, H.-B. Kim, J.-H. Ahn, J. H. Baeck, J. Noh, K.-S. Park, S.-Y. Yoon, and S. Oh*, "Enhancing InGaZnO transistor current through high- dielectrics and interface trap extraction using single-pulse charge pumping," Sci. Rep. 15, 23113, July 2, 2025. doi.org/10.1038/s41598-025-07995-3

J. H. Lee, K. Kim, K. Rim, S. Chong, H. Cho, and S. Oh*, "Impact of Strain on Sub-3 nm Gate-all-around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach," IEEE J. Electron Devices Soc. vol. 12, pp. 770-774, Dec. 2024. doi.org/10.1109/JEDS.2024.3459872 

S. H. Kim, M. Kim, J. H. Lee, K. Kim, J. S. Park*, J. H. Lim*, and S. Oh*, "Optimizing Length Scalability of InGaZnO Thin‐Film Transistors through Lateral Carrier Profile Engineering and Negative ΔL Extension Structure," Adv. Electron. Mater. vol. 10, 2400012, Oct. 2024. doi.org/10.1002/aelm.202400012 

T. Lee, J.-S. Park, and S. Oh*, "Effect of sputtering working pressure on the reliability and performance of amorphous indium gallium zinc oxide thin film transistors," AIP Advances, vol. 14(3), 035145, March 1, 2024. doi.org/10.1063/5.0188437

T. Lee, S. Oh*, "Improvement of Amorphous InGaZnO Thin Film Transistor Reliability and Electrical Performance Using ALD SiO2 Interfacial Layer on PECVD SiO2 Gate Insulator," IEEE Trans. Electron Device. vol. 71, no. 3, pp. 1926-1931, March 2024. doi.org/10.1109/TED.2024.3355025

J. Park, S. Choi, C. Kim, H. J. Shin, Y. S. Jeong, J. U. Bae, C. H. Oh, S. Oh*, and D. H. Kim*, "Lifetime estimation of thin-film transistors in organic emitting diode display panels with compensation," Sci. Rep. 13, 17590, pp. 1-10, Oct. 16, 2023. doi.org/10.1038/s41598-023-44684-5 

S. Sin, S. Oh*, "Deterministic field-free voltage-induced magnetization switching with self-regulated precession for low-power memory," Sci. Rep. 13, 16084, pp. 1-9, Sep. 26, 2023. doi.org/10.1038/s41598-023-43378-2

K. Kim, S. H. Kim, M. Kim, J. H. Lim, J. S. Park*, S. Oh*, "Interpretation of Device Characteristics of Wide-Width InGaZnO Transistors for Gate Driver Circuits," IEEE Electron Device Lett. vol. 44, no. 10, pp. 1652-1655, Oct. 2023. doi.org/10.1109/LED.2023.3306287

J. Won, J. Kang, S. Hong, N. Han, M. Kang, Y. Park, Y. Roh, H. J. Seo, C. Joe, U. Cho, M. Kang, M. Um, K.-H. Lee, J.-E. Yang, M. Jung, H.-M. Lee*, S. Oh*, S. Kim*, S. Kim*, "Device-Algorithm Co-Optimization for an On-Chip Trainable Capacitor-Based Synaptic Device with IGZO TFT and Retention-Centric Tiki-Taka Algorithm," Adv. Sci. vol. 10, no. 29, 2303018, Oct. 17, 2023. doi.org/10.1002/advs.202303018

J. Park, S. Choi, C. Kim, H. J. Shin, Y. S. Jeong, J. U. Bae, C. H. Oh, S. Oh*, and D. H. Kim*, "Current Boosting of Self-Aligned Top-Gate Amorphous InGaZnO Thin-Film Transistors under Driving Conditions," Advanced Electronic Materials, 9(3), 2201109, pp. 1-10, Jan. 10, 2023. doi.org/10.1002/aelm.202201109

S. Sin, S. Oh*, "Lateral double magnetic tunnel junction device with orthogonal polarizer for high-performance magnetoresistive memory," Scientific Reports, 12, 19762, pp. 1-8, Nov. 17, 2022. doi.org/10.1038/s41598-022-24075-y 

J. T. Jang, D. Kim, J. H. Baeck, J. U. Bae, J. Noh, S.-W. Lee, K.-S. Park, J. J. Kim, S. Y. Yoon, C. Kim, Y.-S. Kim, S. Oh*, D. H. Kim, ''Cation Composition-Dependent Device Performance and Positive Bias Instability of Self-Aligned Oxide Semiconductor Thin-Film Transistors: Including Oxygen and Hydrogen Effect," ACS Applied Materials and Interfaces, 14(1), 1389-1396, Jan. 3, 2022. doi.org/10.1021/acsami.1c18890

S. Choi, J. Park, S.-H. Hwang, C. Kim, Y.-S. Kim, S. Oh, J. H. Baeck, J. U. Bae, J. Noh, S.-W. Lee, K.-S. Park, J.-J. Kim, S.Y. Yoon, H.-I. Kwon, D. H. Kim, "Excessive Oxygen Peroxide Model-Based Analysis of Positive-Bias-Stress and Negative-Bias-Illumination-Stress Instabilities in Self-Aligned Top-Gate Coplanar In–Ga–Zn–O Thin-Film Transistors," Adv. Electron. Mater. 8(5), 2101062, 1-9, Jan. 7,2022. doi.org/10.1002/aelm.202101062

H.-E. Kim, H.-W. Jang, M. Furuta, J. Yoon, S. Oh, S.-M. Yoon, "Impact of organic inter-layer dielectric for improvement in mechanical flexibility of self-aligned coplanar In-Ga-Zn-O thin-film transistor," Org. Electron. 96, 106223, pp.1-7, June 10, 2021. doi.org/10.1016/j.orgel.2021.106223

K. Kim, J.H. Lee, S. Oh*, "Strain Effect on Performance of Multi-Stacked Gate-All-Around CMOS Inverters," Semicond. Sci. Technol.  35, 125021, pp. 1-6, Oct. 26, 2020. doi.org/10.1088/1361-6641/abbc8e

S. Maeng, H. Kim, G. Choi, Y. Choi, S. Oh, and J. Kim, "Investigation of Electrical Performance and Operation Stability of RF-sputtered InSnZnO (ITZO) Thin Film Transistors by Oxygen-ambient Rapid Thermal Annealing," Semicond. Sci. Technol. 35, 125019, Oct. 23, 2020.  doi.org/10.1088/1361-6641/abbc8f

S. Seo, B.-S. Kang, J.-J. Lee, H.-J. Ryu, S. Kim, H. Kim, S. Oh, J. Shim, K. Heo, S. Oh, J.-H. Park, "Artificial van der Waals hybrid synapse and its application to acoustic pattern recognition," Nat. Comm. vol. 11, 3936, pp. 1-9, Aug. 7, 2020. doi.org/10.1038/s41467-020-17849-3

K.-L. Han, J.-H. Han, B.-S. Kim, H.-J. Jeong, J.-M. Choi, J.-E. Hwang, S. Oh*, and J.-S. Park*, "Organic/inorganic hybrid buffer in InGaZnO transistors under repetitive bending stress for high electrical and mechanical stability," ACS Appl. Mater. Interfaces, vol. 12, pp. 3784-3791, Dec. 27, 2019. doi.org/10.1021/acsami.9b21531

H.-J. Jeong, B.-S. Kim, K.-L. Han, S. Oh*, and J.-S. Park*, “Quantitative analysis of interface trap recovery caused by repetitive bending stress in flexible oxide thin-film transistors,” Jpn. J. Appl. Phys. vol. 58, 050906, pp. 1-4, April 8, 2019.  doi.org/10.7567/1347-4065/ab0736

K. Kim, and S. Oh*, “Strain effectiveness of gate-all-around Silicon transistors with various surface orientations and cross-sections,” J. Semicond. Tech. Sci. vol. 19, no. 1, pp. 24-29, Feb. 2019. doi.org/10.5573/JSTS.2019.19.1.024

S. Seo, S.-H. Jo, S. Kim, J. Shim, S. Oh, J.-H. Kim, K. Heo, J.-W. Choi, C. Choi, S. Oh, D. Kuzum, H.-S. P. Wong, J.-H. Park, “Artificial optic-neural synapse for colored and color-mixed pattern recognition,” Nat. Comm. vol. 9, 5106, pp. 1-8, Nov. 30, 2018. https://doi.org/10.1038/s41467-018-07572-5

K.-L. Han, H.-S. Cho, K.-C. Ok, S. Oh*, and J.-S. Park*, “Comparative study on hydrogen behavior in InGaZnO thin film transistors with a SiO2/SiNx/SiO2 buffer on polyimide and glass substrates,” Electron. Mater. Lett. vol. 14, no. 6, pp. 749-754, July 17, 2018. doi.org/10.1007/s13391-018-0083-5 

H.-J. Jeong, K.-L. Han, K.-S. Jeong, S. Oh*, and J.-S. Park*, “Effects of repetitive mechanical stress on flexible oxide thin-film transistors and stress reduction via additional organic layer,” IEEE Electron Device Lett. vol. 39, no. 7, pp. 971-974, July 2018. doi.org/10.1109/LED.2018.2839267

Y. Shin, S. T. Kim, K. Kim, M. Y. Kim, S. Oh*, and J. K. Jeong*, “The mobility enhancement of indium gallium zinc oxide transistors via low-temperature crystallization using a tantalum catalytic layer,” Sci. Rep., vol. 7, 10885, Sep. 7, 2017. doi.org/10.1038/s41598-017-11461-0

K.-L. Han, K.-C. Ok, H.-S. Cho, S. Oh*, and J.-S. Park*, “Effect of hydrogen on the device performance and stability characteristics of amorphous InGaZnO thin-film transistors with a SiO2/SiNx/SiO2 buffer,” Appl. Phys. Lett., vol. 111, 063502, Aug. 9, 2017. doi.org/10.1063/1.4997926

S. Choi, J. Jang, H. Kang, J.H. Baeck, J. U. Bae, K.-S. Park, S. Y. Yoon, I. B. Kang, D. M. Kim, S.-J. Choi, Y.-S. Kim, S. Oh*, D. H. Kim*, “Systematic decomposition of the positive bias stress instability in self-aligned coplanar InGaZnO thin-film transistors,” IEEE Electron Device Lett. vol. 38, pp. 580-583, May 2017. doi.org/10.1109/LED.2017.2681204

H.-J. Jeong, K.-L. Han, K.-C. Ok, H.-M. Lee, S. Oh*, J.-S. Park*, “Effect of mechanical stress on the stability of flexible InGaZnO thin-film transistors,” J. Inf. Disp. vol. 43, pp. 87-91, Mar. 2017.

D. H. Kim, S. Choi, J. Jang, H. Kang, D. M. Kim, S.-J. Choi, Y.-S. Kim, S. Oh, J. H. Baeck, J. U. Bae, K.-S. Park, S. Y. Yoon, I. B. Kang, “Experimental decomposition of the positive bias temperature stress-induced instability in self-aligned coplanar InGaZnO thin-film transistors and its modeling based on the multiple stretched-exponential functions,” J. Soc. Inf. Display, vol. 25, pp. 98-107, Feb. 2017. 

Y.-S. Lee, D.-W. Choi, B. Shong, S. Oh*, J.-S. Park*, “Low temperature atomic layer deposition of SiO2 thin films using di-isopropylaminosilane and ozone,” Ceram. Int. vol. 43, pp. 2095-2099, Feb. 2017. 

S.-H. Lee, H.-S. Jun, J.-H. Park, W. Kim, S. Oh, J.-S. Park, “Properties of hafnium-aluminum-zinc-oxide thin films for the application of oxide-transistors,” Thin Solid Films, vol. 620, pp. 82-87, Dec. 2016. 

J. Sheng, H.-J. Lee, S. Oh*, J.-S. Park*, “Flexible and high-performance amorphous indium zinc oxide thin-film transistor using low-temperature atomic layer deposition,” ACS Appl. Mater. Interfaces, vol. 8, pp. 33821-33828, Nov. 18, 2016. doi.org/10.1021/acsami.6b11774

S. Oh*, J. H. Baeck, J. U. Bae, K.-S. Park, and I. B. Kang, “Effect of interfacial excess oxygen on positive-bias temperature stress instability of self-aligned coplanar InGaZnO thin-film transistors,” Appl. Phys. Lett. vol. 108, 141604, April 8, 2016. doi.org/10.1063/1.4945404

S. Oh*, J. Bae, K. Park, and I. B. Kang, “Suppression of light influx into the channel region of photosensitive thin-film transistors ,” IEEE Trans. Electron Devices, vol. 62, issue 12, pp. 4057-4062, Dec. 2015.  doi.org/10.1109/TED.2015.2492680

K.-C. Ok, S. Oh*, H.-J. Jeong, J. U. Bae, and J.-S. Park*, “Effect of alumina buffers on the stability of top-gate amorphous InGaZnO thin-film transistors on flexible substrates,” IEEE Electron Device Letters, vol. 36, issue 9, pp. 917-919, Sep. 2015.

S. Oh*, J. H. Baeck, H. S. Shin, J. U. Bae, K. Park, I. B. Kang, “Comparison of top-gate and bottom-gate amorphous InGaZnO thin-film transistors with the same SiO2/a-InGaZnO/SiO2 stack,” IEEE Electron Device Letters, vol. 35, issue 10, pp. 1037-1039, Oct. 2014. doi.org/10.1109/LED.2014.2351492

H. Bae, H. Seo, S. Jun, H. Choi, J. Ahn, J. Hwang, J. Lee, S. Oh, J. Bae, S. Choi, D. H. Kim, D. M. Kim, “Fully current-based sub-bandgap optoelectronic differential ideality factor technique and extraction of subgap DOS in amorphous semiconductor TFTs,” IEEE Trans. Electron Devices, vol. 61, issue 10, pp. 3566-3569, Oct. 2014.  

H. Bae, H. Choi, S. Jun, C. Jo, Y. H. Kim, J. S. Hwang, J. Ahn, S. Oh, J. Bae, S. Choi, D. H. Kim, and D. M. Kim, “Single-scan monochromatic photonic capacitance-voltage technique for extraction of subgap DOS over the bandgap in amorphous semiconductor TFTs,” IEEE Electron Device Letters, vol. 34, issue 12, pp. 1524-1526, Dec. 2013.

J. Park, S. Oh, S. Kim, H.-S. P. Wong, and S. S. Wong, “Impact of III-V and Ge devices on circuit performance,” IEEE Trans. VLSI Systems, vol. 21, issue 7, pp.1189-1200, July 2013. 

S. Oh* and H.-S. P. Wong*, "Technology projections of III-V devices down to 11 nm: importance of electrostatics and series resistance," Electronics Letters, vol. 49, issue 13, pp. 832-833, June 2013.  (Featured article)

H. Bae, H. Choi, S. Oh, D. H. Kim, J. Bae, J. Kim, Y. H. Kim, and D. M. Kim, “Extraction technique for intrinsic subgap DOS in a-IGZO TFTs by de-embedding the parasitic capacitance through the photonic C-V measurement,” IEEE Electron Device Letters, vol. 34, issue 1, pp. 57-59, Jan. 2013.  

L. Wei*, S. Oh*, and H.-S. P. Wong*, “Technology assessment methodology for complementary logic applications based on energy-delay optimization,” IEEE Trans. Electron Devices, vol. 58, issue 8, pp. 2430-2439, August 2011.  

S. Oh* and H.-S. P. Wong*, “Viability study of all-III-V SRAM for beyond-22-nm logic circuits,” IEEE Electron Device Letters, vol. 32, issue 7, pp. 877-879, July 2011. 

S. Oh* and H.-S. P. Wong, “Physics-based compact model for III-V digital logic FETs including gate tunneling leakage and parasitic capacitance,” IEEE Trans. Electron Devices, vol. 58, issue 4, pp. 1068-1075, April 2011.  

S. Oh* and H.-S. P. Wong, “A physics-based compact model of III-V FETs for digital logic applications: current-voltage and capacitance-voltage characteristics,” IEEE Trans. Electron Devices, vol. 56, issue 12, pp.2917-2924, Dec. 2009.  

S. Oh*, and H.-S. P. Wong, “Effect of parasitic resistance and capacitance on performance of InGaAs HEMT digital logic circuits,” IEEE Trans. Electron Devices, vol. 56, issue 5, pp.1161-1164, May 2009. 

J.-H. Yi, S. Oh, H.-S. P. Wong, “Hole mobility characteristics under electrical stress for surface-channel germanium transistors with high-k gate stack,” Japanese Journal of Applied Physics, vol. 47, issue 4, pp. 2544-2547, April 25, 2008. 

S. Sin, S. Oh, "Energy-Efficient Voltage-Induced Self-Regulated Precessional MRAM with Low Write Error Rate <10^-9,"  in the 9th Electron Devices Technology and Manufacturing (EDTM 2025), paper TP-60, Hong Kong, China, March 11, 2025.

J. H. Park, M. G. Yun, K. Kim, J. M. Jang, J. H. Baeck, W. S. Ryu, J. Noh, K. S. Park, and S. Oh, "Classification of Interface Traps in InGaZnO Thin Film Transistors by Emission Time Constant Decomposition," in the 24th International Meeting on Information Display (IMID 2024), paper P1-023, Jeju, Korea, Aug. 21, 2024.

S. H. Kim, H.-D. Kim, J. S. Park, and S. Oh, "Vertical Thin-Film Transistor with Parasitic Capacitance Reduction Structure for High-Resolution XR Display," in the 24th International Meeting on Information Display (IMID 2024), paper P1-023, Jeju, Korea, Aug. 21, 2024.

T. Lee, S. Oh, "Advantages of Using Interfacial Gate Dielectric ALD Layer in InGaZnO Thin-Film Transistor for Hydrogen Diffusion Control," in the 18th International Thin-Film Transistor Conference (ITC 2024), Daejeon, Korea, March 27-2, 2024.

S. H. Kim, K. Kim, S. Oh, "Modeling of Anomalous Dimension-Dependent Effect in IGZO TFTs Caused by Random Potential Distribution," in the 18th International Thin-Film Transistor Conference (ITC 2024), Daejeon, Korea, March 27-2, 2024.

J.-H. Park, K. Kim, H.-B. Bae, J.-H. Ahn, J. H. Baeck, J. Noh, K.-S. Park, and S. Oh, "Drive Current Enhancement of InGaZnO Thin-Film Transistors by Adoption of High-k Gate Dielectric Materials," in the 23rd International Meeting on Information Display (IMID 2023), paper P1-053, Busan, Korea, Aug. 23, 2023.

J H. Lee, K. Kim, K. Rim, S. Chong, H. Cho, S. Oh, "Performance Evaluation of Strain Effectiveness of Sub-5 nm GAA FETs with Compact Modeling Based on Neural Networks," in the 7th Electron Devices Technology and Manufacturing (EDTM 2023), paper 45D-4, Seoul, Korea, March 9, 2023.

S. Sin, S. Oh, "Novel Field-Free, Shape-Assisted Ferromagnet Switching Using VCMA Effect," in the 7th International Conference on Electronic Materials and Nanotechnology for Green Environment (ENGE 2022), paper 13-2377, Jeju, Korea, Nov. 8, 2022.

S. H. Kim, K. Kim, J. S. Park, J. H. Lim, S. Oh, "Wide-Width Effects of Oxide TFTs," in the 7th International Conference on Electronic Materials and Nanotechnology for Green Environment (ENGE 2022), paper 5-3430, Jeju, Korea, Nov. 9, 2022.

K. Kim, T. Lee, K. H. Ji, J. H. Baeck, J. Noh, K.-S. Park, S. Oh, "High-Speed, Real-Time Extraction of Traps in Oxide Thin Film Transistors" in the 7th International Conference on Electronic Materials and Nanotechnology for Green Environment (ENGE 2022), paper 5-2562, Jeju, Korea, Nov. 9, 2022.

K. Kim, S. H. Kim, M. Kim, J. S. Park, J. H. Lim, S. Oh, "Interpretation of Channel Width-Dependent Shift in Device Characteristics of Oxide Semiconductor Thin-Film Transistors,"  in International Meeting on Information Display (IMID), paper P1-060, Korea, Aug. 24, 2022.

J. S. Lee, and S. Oh, "Universal Relationship between PECVD SiO2 Gate Insulator Film Properties and a-ITZO TFT Characteristics," in 29th Korean Conference on Semiconductors, TP1-281, January 25, 2022.

M. Kim, K. Kim, J. S. Park, J. H. Lim, and S. Oh, "Device Design of InGaZnO Floating Gate Thin-film Transistors for Threshold Voltage Control at Short Channel Lengths," in 29th Korean Conference on Semiconductors, TP1-282, January 25, 2022.

S.M. Yu, T. Lee, K. Kim, and S. Oh, "Ferroelectric TFT synaptic device and array for spiking neural networks," in 28th Korean Conference on Semiconductors, paper FD2-H4, January 29, 2021.

S. Oh, "[Invited] Stability of InGaZnO Thin-Film Transistors for Displays and Hybrid Applications," in the 6th International Conference on Electronic Materials and Nanotechnology for Green Environment (ENGE 2020), paper 4-0320, Jeju, Korea, Nov. 3, 2020.

S. Oh, S.H. Kim, M. Kim, S.M. Yu, Y. Choi, "(Invited) Device scalability of InGaZnO TFTs for Next-Generation Displays," in Pacific Rim Meeting on Electrochemical and Solid State Science (PRIME 2020), paper H03-1920, Oct. 4-9, 2020.

S. H. Kim, S. M. Yu, M. Kim, K. Kim, J. S. Park, J. H. Lim, S. Oh, "Device Scalability of TFTs down to 1μm Channel Length,"  in International Meeting on Information Display (IMID), paper 02_05_1467, Korea, Aug. 25-28, 2020.

K. Kim, T. Lee, Y. Choi, J. Lee, T. Seok, T. J. Park, S. Oh, "InGaZnO Synaptic Device with Charge-Trapping Layer under Illumination Conditions for Unsupervised Spiking Neural Networks," in International Meeting on Information Display (IMID), paper 03_07_1584, Korea, Aug. 25-28, 2020.

Y. Choi, K. Kim, S. Kim, S. Oh, "Understanding NBIS Mechanism of a-IGZO TFTs by Pulsed Stress Measurements Using Various Voltage and Light Pulse Widths," in 27th Korean Conference on Semiconductors, paper FC3-H-4, February 14, 2020.

Y. Choi, K. Kim, S. Maeng, J. Kim, S. Oh, “Dynamics of Positive Charge Trapping in a-IGZO TFTs under NBIS Using Microsecond Pulsed Light Illumination,” in International Meeting on Information Display (IMID), paper B02-4, Gyeongju, Korea, Aug. 27-30, 2019.

S. Maeng, Y. Choi, K. Kang, S. Oh, J. Kim, “Improvement of Electrical Properties and Stability of ITZO(Indium-Tin-Zinc-Oxide) TFT(Thin Film Transistor) Using Oxygen Rapid Thermal Annealing,” in International Meeting on Information Display (IMID), P02-33, Gyeongju, Korea, Aug. 27-30, 2019.

H. -W. Jang, K. Kim, S. Oh, S. -M. Yoon, “Analysis on Mechanical-Strain Induced Bias-Stress Instabilities for the Flexible InGaZnO Thin Film Transistors with Different Channel Geometries,” in 26th International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD), paper 4-2, Kyoto, Japan, July 2-5, 2019. 

S. Oh, “[Invited] Structure, stability, and applications of InGaZnO thin-film transistors,” in 26th Korean Conference on Semiconductors, paper TH2-H-1, February 13-15, 2019.

J.H. Lee, K. Kim, S. Oh, “Stress analysis of sub-7nm P- and NMOS gate-all-around transistor processes on Si bulk and SiGe-on-insulator substrates,” in 26th Korean Conference on Semiconductors, paper TB1-G-2, February 13-15, 2019.

K. Kim, J.H. Lee, S. Oh, “Logic Performance of Multi-Stacked Gate-All-Around CMOS Transistors with Strain Incorporation,” in 26th Korean Conference on Semiconductors, paper TB1-G-3, February 13-15, 2019. 

K.-L. Han, H.-J. Jeong, B.-S. Kim, S. Oh, J.-S. Park, "A study on degradation mechanism of flexible a-InGaZnO thin film transistor under repetitive bending stress using simulation," in 25th International Display Workshops (IDW), paper AMDp1-4, Nagoya, Japan, December 12-14, 2018.

S. Oh, K. Kim, J.H. Lee, “[Invited] Strain effectiveness of gate-all-around field-effect transistors,” in 2018 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), paper B5-2, Kitakyushu, Japan, July 2-4, 2018.

J. T. Jang, H. R. Yu, G. Ahn, S.-J. Choi, D. M. Kim, Y.-S. Kim, S. Oh, J. H. Baeck, J. U. Bae, K.-S. Park, S. Y. Yoon, I. B. Kang, D. H. Kim, “Universal method to determine the dynamic NBIS- and PBS-induced instabilities on self-aligned coplanar InGaZnO thin-film transistors,” SID (Society for Information Display) International Symposium Digest of Technical Papers, vol. 49, pp. 232-235, May 2018.

K. Kim, S. Oh, “Strain effectiveness of gate-all-around Si transistors with various surface orientations and cross-sections,” in the 25th Korean Conference on Semiconductors (KCS), paper WG2-G-6, Jeongseon, Korea, Feb. 5-7, 2018.

D. H. Kim, S. Choi, J. Jang, H. Kang, D. M. Kim, S.-J. Choi, Y.-S. Kim, S. Oh, J. H. Baeck, J. U. Bae, K.-S. Park, S. Y. Yoon, I. B. Kang, “[Invited] Experimental Decomposition of the Positive Gate-bias Temperature Stress-induced Instability and Its Modeling in InGaZnO Thin-film Transistors,” in International Meeting on Information Display (IMID), paper E37-1, Busan, Korea, August 28-31, 2017.

J.-H. Baeck, S. Oh, D. Lee, T. Park, J. U. Bae, K.-S. Park, S.-Y. Yoon, I. B. Kang, “21-3: Reliability of Coplanar Oxide TFTs : Analysis and Improvement,” SID (Society for Information Display) International Symposium Digest of Technical Papers, vol. 48, pp. 294-296, May 2017.

D. H. Kim, S. Choi, J. Jang, H. Kang, D. M. Kim, S.-J. Choi, Y.-S. Kim, S. Oh, J. H. Baeck, J. U. Bae, K.-S. Park, S. Y. Yoon, I. B. Kang, “21-4: Distinguished Paper: Experimental Decomposition of the Positive Bias Temperature Stress-induced Instability in Self-aligned Coplanar InGaZnO Thin-film Transistors and its Modeling based on the Multiple Stretched-exponential Functions,” SID (Society for Information Display) International Symposium Digest of Technical Papers, vol. 48, pp. 298-301, May 2017.

S. Oh, J. U. Bae, K.-S. Park, S.-Y. Yoon and I. B. Kang, “Analysis on light propagation into InGaZnO thin-film transistors,” in International Meeting on Information Display (IMID), paper B26-2, Jeju, Korea, August 23-26, 2016.

D. Lee, J. H. Baeck, T. Park, S. Oh, J. U. Bae, K.-S. Park, S.-Y. Yoon, “Analysis on PBTS stability improvement in self-aligned coplanar InGaZnO thin film transistors,” in International Meeting on Information Display (IMID), paper B42-5, Jeju, Korea, August 23-26, 2016.

J. Jeon, S. M. Lee, J. Jang, S. Oh, J. Bae, K. Park, and I. Kang, “Mechanical stability for coplanar a-IGZO TFTs on plastic substrate,” in International Meeting on Information Display (IMID), paper 28-2, Daegu, Korea, August 18-21, 2015.

D. Lee, J. H. Baeck, T. Park, S. Oh, J. Bae, K. Park, and I. Kang, “Analysis of PBTS instability of self-aligned coplanar InGaZnO thin film transistors,” in International Meeting on Information Display (IMID), paper 41-5, Daegu, Korea, August 18-21, 2015.

K. -S. Park, S. Oh, P. Yun, J. U. Bae, and I. B. Kang, “Prospects of oxide TFTs approaching LTPS (Invited),” in Active-Matrix Flatpanel Displays and Devices (AM-FPD), pp.241-244, Kyoto, Japan, July 1-4, 2015.

S. Oh, J.-H. Baeck, D. Lee, T. Park, H. S. Shin, J. U. Bae, K.-S. Park, and I. Kang, “Improvement of PBTS stability in self-aligned coplanar a-IGZO TFTs,” in SID (Society for Information Display) International Symposium, San Jose, USA, June 2-5, 2015.

J.-H. Baeck, S. Oh, H. Shin, J. Bae, K. Park, I. Kang, “[Invited] Analysis of hydrogen effect in a-InGaZnO thin film transistors,” in International Meeting on Information Display (IMID), paper 23-2, Daegu, Korea, August 26-29, 2014.

S. Oh, J. -H. Baeck, H. S. Shin, J. U. Bae, W. Shin, I. Kang, “Effect of annealing on oxygen content in SiO2/a-IGZO/SiO2 stacks,” in International Display Workshops (IDW), paper AMD5-4L, Sapporo, Japan, December 4-6, 2013.

H. S. Shin, S. M. Lee, S. Oh, J. -U. Bae, W. Shin, I. B. Kang, “High performance top-gate oxide TFT on plastic substrate for flexible OLED displays,” in International Display Workshops (IDW), paper FLX6-1L, Sapporo, Japan, December 4-6, 2013.

S. Oh, L. Wei, S. Chong, J. Luo, H.-S. P. Wong, “Device and circuit interactive design and optimization beyond the conventional scaling era,” Invited Special Session Paper, IEEE International Electron Devices Meeting (IEDM), paper 17.3, San Francisco, CA, December 6-8, 2010.

S. Oh, J. Park, S. Wong, H.-S. P. Wong, “Modeling and analysis of III-V logic FETs for devices and circuits: sub-22nm technology III-V SRAM cell design,” International Symposium on Quality Electron Design (ISQED), pp. 342-346, San Jose, CA, March 22-24, 2010.

L. Wei, S. Oh, and H.-S. P. Wong, “Performance benchmarks for Si, III-V, TFET, and carbon nanotube FET – Re-thinking the technology assessment methodology for complementary logic applications,” IEEE International Electron Devices Meeting (IEDM), Tech. Dig., pp. 16.2.1-16.2.4, San Francisco, CA, December 2010.

H.-S. P. Wong, L. Wei, S. Oh, A. Lin, J. Deng, S. Chong, K. Akarvardar, “Technology projection using simple compact models,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 1-8, San Diego, CA, Sept. 9-11, 2009.

S. Oh and H.-S. P. Wong, “Physics-based compact model of III-V heterostructure FETs for digital logic applications,” IEEE International Electron Devices Meeting (IEDM), Tech. Dig., pp. 883-886, San Francisco, CA, December 15-17, 2008.

J.-H. Yi, S. Oh, H.-S. P. Wong, “Electrical stress effects on mobility of germanium-on-insulator (GeOI) pMOSFETs with HfO2 gate dielectric,” International Conference on Solid State Devices and Materials (SSDM), pp. 34-35, Tsukuba, Ibaraki, Japan, September 19-21, 2007.

A. Pethe, T. Krishnamohan, D. Kim, S. Oh, H.-S. P. Wong and K. C. Saraswat, “Investigation of performance limits of III-V double-gate n-MOSFETs,” IEEE International Electron Devices Meeting (IEDM), Tech. Dig., pp. 605-608, Dec. 5, 2005.

S. Sin, S. Oh. "스핀 홀 효과 기반의 비휘발성 스핀트로닉스 시냅스 소자," Patent No. 10-2025-0113978 (filed on Aug. 18, 2025).

S. Oh, J. H. Park, T. Lee, "3차원 반도체 메모리 소자 및 그 제조 방법," Patent No. 10-2025-0097896 (filed on July 21, 2025)

S. Sin, S. Oh, "전압제어 자기 이방성 효과를 이용한 자기터널접합 소자 및 그 제조 방법," Patent No. 10-2025-0002354 (filed on Jan. 7, 2025).

J. S. Park, S. Oh, S. H. Kim, T. Lee, M. H. Kim, J. H. Lim, "트랜지스터 및 이를 포함하는 표시패널(TRANSISTOR AND DISPLAY PANEL INCLUDING SAME)," Patent No. 10-2022-0166919 (filed on Dec. 2, 2022). US Patent No. 18/242,005 (filed on Sep. 5, 2023).

J. I. Hong, T. Na, S. Oh, "스핀 전하 변환 기반의 스핀 로직 소자(SPIN-CHARGE CONVERSION BASED SPIN LOGIC DEVICE),"  Patent No. 10-2022-0152325 (filed on Nov. 15, 2022), Reg. No. 10-2649376 (issued on March 14, 2024).  US Patent No. 18/151,678 (filed on Jan. 9, 2023).

J. S. Park, S. Oh, S. H. Kim, T. Lee, H. Choi, J. H. Lim, "표시 장치(Display Device)," Patent No. 10-2022-0096802 (filed on Aug. 3, 2022). US Patent No. 18/312,637 (filed on May 5, 2023).

S. Sin, S. Oh, "고속 고에너지효율 자기터널접합 소자(High-speed and high-energy-efficiency magnetic tunnel junction device)," Patent No. 10-2022-0082429 (filed on July 5, 2022). PCT Patent No. PCT/KR2023/009455 (filed on July 5, 2023). Reg. No. 10-2601744 (issued on Nov. 6, 2023)

J. S. Park, S. Oh, K. Kim, M. H. Kim, M. Kim, J. H. Lim, "표시 장치와 표시 장치의 제조 방법(DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME)," Patent No. 10-2022-0011646 (filed on Jan. 26, 2022). Japan Patent No. 2022-131116 (filed on Aug. 19, 2022). US Patent No. 17/938,658 (filed on Oct. 6, 2022). China Patent No. 202310063233.5, CNU No. 202320115126.8 (filed on Jan. 19, 2023), CNU Reg. No. CN219321354U (issued on July 7, 2023).

G. C. Park, S. Oh, K. Kim, J. S. Park, J. H. Lee, J. H. Lim, "디스플레이 장치 및 그 제조방법(Display apparatus and method of manufacturing the same) ," Patent No. 10-2020-0168714 (filed on Dec. 4, 2020).

H. Choi, S. Oh, K. Kim, J.S. Park, J. H. Lee, J. H. Lim, "표시 장치(DISPLAY DEVICE) ," Patent No. 10-2020-0119880 (filed on Sep. 17, 2020). US Patent No. 17/232,211 (filed on April 16, 2021). US Patent Reg. No. 11,894,393 (issued on Feb. 06, 2024). China Patent No. 202111061244.7 (filed on Sep. 10, 2021).

S. Oh, S. Kim, "Synapse-Mimetic Device Capable of Neural Network Training(신경망 훈련이 가능한 시냅스 모방 소자)," PCT Patent No. PCT/KR2020/006613 (filed on May 21, 2020). US Patent No. 17/610,027 (filed on November 9, 2021).

J. S. Park, S. Oh, J. H. Lim, S. H. Kim, Y. J. Choi, "표시 장치와 그의 제조 방법(DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME)," Patent No. 10-2020-0084618 (filed on July 9, 2020). US Patent No. 17/367,198 (filed on July 2, 2021). US Patent Reg. No. 11,764,231 (issued on Sep. 19, 2023). China Patent No. 202110775372.1 (filed on July 9, 2021). Europe Patent No. 21184336.2 (filed on July 7, 2021).

J. S. Park, S. Oh, M. H. Kim, S. H. Kim, Y. J. Choi, J. H. Lim, "표시장치(DISPLAY DEVICE)," Patent No. 10-2020-0081468 (filed on July 2, 2020). Reg. No. 10-2758297 (issued on Jan. 17, 2025). US Patent No. 17/206,189 (filed on March 19, 2021). China Patent No. 202110749364.X (filed on July 2, 2021).

S. W. Sohn, S. Oh, J. S. Park, Y. J. Choi, S. H. Kim, J.H. Lim, "표시 장치와 그의 제조 방법(DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME)," Patent No. 10-2020-0077987 (filed on June 25, 2020). Reg. No. 10-2839061 (issued on July 23, 2025). China Patent No. 202110696703.2 (filed on June 23, 2021). Europe Patent No. 21181074.2 (filed on June 23, 2021).

• "Display device including an interlayer insulating layer selectively overlapping an active layer of a driving transistor and method for manufacturing the same," US Patent No. 17/313,046 (filed on May 6, 2021).  US Patent Reg. No. 11,930,670 (issued on Mar. 12, 2024).

• "Method for manufacturing display device including second interlayer insulating layer overlapping active layer of driving transistor and not overlapping active layer of switching transistor," US Patent No. 18/434,812 (filed on Feb. 7, 2024). US Patent Reg. No. 12,324,322 (issued on Jun. 3, 2025)

J. I. Hong, S. Oh, "Spin logic device based on spin-charge conversion and spin logic array using the same," US Patent No. 16/875,415 (filed on May 27, 2020). US Patent Reg. No. 11,785,783 (issued on 2023.10.10).  

• Continuation Application: US Patent No. 18/455,449 (filed on Aug. 24, 2023). US Patent Reg. No. 12,382,641 (issued on 2025.08.05)

S. Oh, S. Kim, "신경망 훈련이 가능한 시냅스 모방 소자(Synaptic device for neural network training)", Patent No. 10-2020-0021308 (filed on Feb. 20, 2020). Reg. No. 10-2490774 (issued on Jan. 17, 2023).

S. Oh, J. I. Hong, "스핀 로직 소자 및 이의 동작 방법(Spin logic device and method of operating the same)", Patent No. 10-2020-0021311 (filed on Feb. 20, 2020), Reg. No. 10-2216981 (issued on Feb. 10, 2021).

J. I. Hong, S. Oh, "스핀-전하 변환 기반의 스핀 로직 소자 및 그를 이용한 스핀 로직 어레이(Spin Logic Device Based on Spin-Charge Conversion and Spin Logic Array)", Patent No. 10-2020-0005462 (filed on Jan. 15, 2020), Reg. No. 10-2302781 (issued on Sep. 9, 2021)

J. I. Hong, S. Oh, "스핀-전하 변환 기반의 스핀 로직 소자 및 그 동작 방법(Spin logic device based on spin-charge conversion and method of operation thereof)", Patent No. 10-2019-0099458 (filed on Aug. 14, 2019), Reg. No. 10-2250755 (issued on May 4, 2021)

S. Oh et al. "THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME," US Patent No. 16/221203 (filed on 2018.12.14).

S. Oh et al. "Thin film transistor substrate having two different types of thin film transistors on the same substrate and display using the same," US Patent No. 16221203 (filed on 2018.12.14),  US Patent Reg. No. 11,107,870 (issued on 2021.08.31).

J. Baeck, J. Bae, S. Oh, T. Park, "Thin-film transistor array substrate," US Patent No. 16210934 (filed on 2018.12.05), US Patent Reg. No. 10,692,975 (issued on 2020.06.23)

J.-H. Baeck, J. Bae, S. Oh, D. Lee, T. Park, “박막트랜지스터 어레이 기판(Array substrate for thin film transistor),” Patent No. 10-2015-0179783 (filed on December 16, 2015), Reg. No. 10-2518392 (issued on March 31, 2023). US Patent No. 15/531952 (filed on 2015.12.16), US Patent Reg. No. 10,192,957 (issued on Jan. 29, 2019). Divisional Patent No. 10-2023-0042919 (filed on 2023.03.31). Reg. No. 10-2699702 (issued on Aug. 23, 2024).

S. Oh et al., “박막 트랜지스터 기판 및 이를 이용한 표시장치 (Thin film transistor substrate and display using the same),” Patent No. 10-2015-0115995 (filed on July 10, 2015), Reg. No. 10-2467574 (issued on Nov. 11, 2022). US Patent No. 14/838564 (filed on August 28, 2015), US Patent Reg. No. 10,083,990 (issued on Sep. 25, 2018). China Patent No. 201510536285.5 (filed on August 27, 2015). Divisional Patent No. 10-2022-0150034 (filed on Nov. 11, 2022). Reg. No. 10-2659940 (issued on April 18, 2025)

S. Oh et al., “Thin film transistor substrate and display using the same,” Patent No. 10-2015-0113274 (filed on August 11, 2015), Reg. No. 10-2360788 (issued on Feb. 4, 2022). US Patent No. 14/838659 (filed on August 28, 2015), US Patent Reg. No. 10,181,502 (issued on Jan. 15, 2019). China Patent No. 201510536285.5 (filed on August 27, 2015). Divisional Patent No. 10-2022-0150034 (filed on Nov. 11, 2022), Reg. No. 10-2659940 (issued on April 18, 2025)

S. Oh et al., “Thin film transistor substrate and display using the same,” Patent No. 10-2015-0113281 (filed on July 9, 2015), Reg. No. 10-2370322 (issued on Feb. 28, 2022). US Patent No. 14/838631 (filed on August 28, 2015), US Patent Reg. No. 09,691,833 (issued on June 27, 2017). China Patent No. 201510536295.9 (filed on August 27, 2015).

S. Oh, "Thin Film Transistor Substrate And Display Using The Same," Patent No. 10-2015-0026007 (filed on 2015.02.24), Reg. No. 10-2251176 (issued on May 6, 2021)

S. Oh, “Thin film transistor substrate and display using the same,” Patent No. 10-2015-0026014 (filed on February 9, 2015), Reg. No. 10-2279392 (issued on July 14, 2021).

J.-H. Baeck, J. Bae, S. Oh, D. Lee, “Oxide semiconductor thin film transistor substrate having hydrogen supplying thin layer,” Patent No. 10-2014-0170884 (filed on September 29, 2014), Reg. No.  10-23161-3 (issued on Oct. 18, 2021).

S. Park, S. Oh, P. Yoon, J. Park, “Oxide semiconductor thin film substrate,” Patent No. 10-2014-0170588 (filed on September 21, 2014), Reg. No. 10-2316102 (issued on Oct. 18, 2021)

S. Oh et al., “Display device and fabricating method thereof,” Patent No. 10-2014-0114308 (filed on August 29, 2014).

S. Oh, “Display device and fabricating method thereof,” Patent No. 10-2014-0114307 (filed on August 29, 2014).

S. Oh et al., “Display device and fabricating method thereof,” Patent No. 10-2014-0114306 (filed on August 29, 2014).

S. Lee, S. Oh, H. Shin, J. Jeon, D. Lee, “Display device and method for manufacturing the same,” Patent No. 10-2014-0114304 (filed on August 29, 2014). 

J. Jeon, S. Lee, S. Oh, J.-H. Baeck, D. Lee, “Display device and method for manufacturing the same,” Patent No. 10-2014-0114302 (filed on August 29, 2014), Reg. No. 10-2423800 (issued on July 18, 2022). Divisional Patent No. 10-2022-0025881 (filed on Feb. 28, 2022), Reg. No. 10-2423800 (issued on July 18, 2022).

S. Oh et al., “Thin film transistor array substrate and display device including same,” Patent No. 10-2014-0145421 (filed on August 12, 2014).

S. Oh et al., “Oxide semiconductor thin film transistor and array substrate for display device having the same,” Patent No. 10-2014-0089375 (filed on July 15, 2014), Reg. No. 10-2182482 (issued on Nov. 18, 2020).

S. Oh et al., “Display device,” Patent No. 10-2014-0021492 (filed on February 24, 2014).

J. Seo, S. Oh, “Array substrate,” Patent No. 10-2013-0150068 (filed on December 4, 2013), Reg. No. 10-2207941 (issued on Jan. 20, 2021).

S. Oh et al., “Oxide semiconductor thin film transistor, method for fabricating TFT, array substrate for display device having TFT and method for fabricating the same (산화물 반도체 박막 트랜지스터, 제조방법 및 이를 구비한 표시장치용 어레이 기판 및 제조방법),” Patent No. 10-2013-0075904 (filed on June 28, 2013), Reg. No. 10-2068089 (issued on Jan. 14, 2020).

S. Oh et al., “Thin film transistor substrate having metal oxide semiconductor (금속 산화물 반도체를 포함하는 박막 트랜지스터 기판)”, Patent No. 10-2013-0022117 (filed on February 28, 2013), Reg. No. 10-1421288 (issued on July 14, 2014).

S. Oh, “Display device and manufacturing method thereof”, Patent No. 10-2013-0015455 (filed on February 13, 2013), Reg. No. 10-2087029 (issued on March 4, 2020).

S. Oh, “Oxide thin film transistor capable of reducing leakage current and a method for fabricating the same (산화물 박막 트랜지스터 및 이의 제조 방법)”, Patent No. 10-2012-0022738 (filed on March 6, 2012), Reg. No. 10-1950834 (issued on Feb. 21, 2019).

J. Kim, S. Park, J. Lim, M. Kim, S. Oh, “Transistor, a manufacturing method thereof, a display device including the same, and a method for manufacturing the display device capable of preventing the deterioration of image quality due to the malfunction of the transistor”, Patent No. 10-2011-0079868 (filed on August 10, 2011).

J. Kim, S. Park, J. Lim, M. Kim, S. Oh, “Nano structure, a method for fabricating a nano structure, a photoelectronic device and a photoelectronic device package capable of reducing process time”, Patent No. 10-2011-0065127 (filed on June 30, 2011), Reg. No. 10-1807877 (issued on Dec. 5,  2017).

J. Kim, S. Park, J. Lim, M. Kim, S. Oh, “Photoelectric device and a manufacturing method thereof capable of converting light energy into electric energy”, Patent No. 10-2011-0050332 (filed on May 26, 2011).

J. Kim, S. Park, J. Lim, M. Kim, S. Oh, “Solar cell and a manufacturing method thereof for a plurality of cells which are connected in parallel”, Patent No. 10-2011-0048473 (filed on May 23, 2011), Reg. No. 10-1734567 (issued on May 2, 2017).