EWiC: Emulation of Wireless Communication among Chiplets inside a Computing System
A project funded by the European Research Council (ERC)
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The EWiC project is designing and developing the first-ever emulation of wireless communication among chiplets inside a computing system. Funded by the ERC Proof of Concept program, EWiC builds on our ERC Starting Grant WINC to experimentally validate a novel hybrid communication architecture that combines wired and wireless links. This innovation addresses growing bottlenecks in chiplet-based computing and promises significant speedups in emerging AI and data-intensive workloads. By bridging the gap between simulation and real hardware, EWiC aims to unlock new commercial and research opportunities, positioning Europe at the forefront of advanced computing technologies.
Motivation
Motivation
As computing shifts from monolithic chips to modular, chiplet-based architectures, efficient communication between chiplets has become a critical challenge. Wired interconnects are increasingly limited by fixed routing, energy inefficiencies, and I/O constraints, especially as systems scale to meet the demands of AI and high-performance applications. Wireless links offer complementary benefits: one-hop communication, native broadcasting, and adaptability, but cannot fully replace wires due to bandwidth limitations. EWiC introduces a hybrid wired-wireless communication model that combines the strengths of both. This approach promises significantly improved performance, energy efficiency, and scalability, and could enable breakthroughs in domains ranging from drug discovery to autonomous systems. By demonstrating this technology through emulation, EWiC seeks to de-risk its adoption, validate performance gains, and pave the way for its commercialization in a rapidly growing chiplet market.
Objectives
Objectives
EWiC aims to demonstrate the first emulation of wireless communication among chiplets using a hybrid wired-wireless architecture. The project will develop a hardware emulator where FPGAs act as chiplets running real CPU and AI accelerator designs, interconnected via both high-speed wired links and Software-Defined Radios (SDRs) functioning as wireless transceivers. This setup will replicate realistic communication conditions and validate previous simulation-based findings from the ERC Starting Grant WINC, targeting at least a 2× performance improvement. The SDR-based wireless layer will showcase dynamic reconfiguration, broadcast capability, and low-latency communication across chiplets. Alongside the technical implementation, EWiC will explore the commercial potential of the technology by engaging stakeholders, conducting market analysis, and establishing a patent strategy to protect key innovations. The project will deliver a validated prototype and a clear exploitation roadmap, paving the way for Europe to lead in high-performance, energy-efficient, and scalable chiplet-based computing systems.
EWIC in a nutshell
EWIC in a nutshell
Principal Investigator
Principal Investigator
Abhijit Das is the Principal Investigator of EWiC. He is a Director of Research and Group Leader with the NaNoNetworking Center in Catalunya (N3Cat) at UPC. Before this role, he was a Post-Doctoral Researcher with the TARAN team at INRIA. Earlier in his career, he briefly worked as a Senior Silicon Design Engineer at AMD, contributing to the performance modelling team responsible for the Zen microarchitecture. Abhijit was honoured with the Best PhD Thesis Award in Computer Science & Engineering from the Indian Institute of Technology (IIT) Guwahati, India. His dissertation focused on designing data-aware chip-scale networks to enhance the performance of many-core systems. Abhijit's research primarily revolves around Computer Architecture, with current projects aimed at developing efficient chip and package-scale networks, caches, and Deep Neural Network (DNN) accelerators. His video tutorials on using the gem5 simulator are among the most popular on YouTube, garnering over 35K views. He also created and maintains CA Deadlines, a website that provides countdowns to top Computer Architecture conference deadlines. Abhijit is a professional member of the IEEE and ACM, and an affiliate member of the HiPEAC.
Website: https://abhijitcse.github.io/
Contact: abhijit.das@upc.edu
Co-Principal Investigator
Co-Principal Investigator
Sergi Abadal is the Co-Principal Investigator of EWiC. He received the PhD in Computer Architecture from the Universitat Politècnica de Catalunya (UPC), Barcelona, Spain, in July 2016, where he also had obtained the MSc in Telecommunication Engineering in 2011. He has also held several visiting researcher positions, including Georgia Tech in 2009, University of Illinois at Urbana-Champaign in 2015/2017/2019, and the Foundation of Research and Technology Hellas in 2018. Currently, Sergi is the director of the Nanonetworking Center in Catalunya (N3Cat) and distinguished researcher at the Computer Architecture Department at UPC, acting as coordinator and principal investigator of projects such as the ERC Starting Grant WINC or H2020 FET-Open WIPLASH. He is also Area Editor of multiple journals such as the IEEE Transactions on Mobile Computing or the Nano Communication Networks (Elsevier) Journal, where he was selected Editor of the Year 2019. He also acts as one of the ambassadors the European Innovation Council (EIC) through its program of National Champions. He has published over 150 papers in top journals and conferences, and contributed in the organization of over 25 conferences and workshops. Sergi is member of the IEEE, ACM, and HiPEAC.
Website: www.sergiabadal.com
Contact: abadal@ac.upc.edu
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