The purpose of this project was to test and strengthen my knowledge of different types of digital circuits and the tradeoffs that come with them. To determine which version of 3 to 8 row address decoder was the best(considering speed, leakage, etc.), my partner and I designed three different decoders consisting of inverters and 2 or 3 input NAND and NOR logic gates using NMOS and PMOS transistors and cadence software.
Testbench used to simulate 3 to 8 row address decoders
To start the project, we tested the speed of the five different logic gates(INV, 2-Input Nand, 3-Input Nand, 2-Input Nor, 3-Input Nor) by using 11 stage ring oscillators. and measuring the frequency. Next, we tested the speed of the our three decoder designs using an LFSR to produce pseudo-random bit values over 7 or more cycles.
2-Nand to 2-Nor - 3.333 MHz
3-Nand to Inverter - 4.761 MHz
3-Nor - 5.0 MHz
Next, we tested the average power for 7 cycles.
2-Nand to 2-Nor - 4.925 nW
3-Nand to Inverter - 6.295 nW
3-Nor - 5.0 MHz 5.775 nW
The next step in our testing and design process was to determine if there was a way to improve the performance of any of our decoders. We attempted to increase the speed of the 3-Nand to Inverter decoder by increasing the Fin size of the transistors, but to no avail. The circuit was unable to surpass the 3 Input Nor in speed regardless of now much we increased the size of the fins. We ran many other tests to optimize lowest power and speed by manipulating the components of the decoders.
2-Nand 2-Nor Decoder
3-Nor Decoder
3-Nand-INV Decoder
2-Nand 2-Nor Decoder Simulation
3-Nor Decoder Simulation
3-Nand -INV Decoder Simulation
Through this project, we learned that many factors contribute to a design’s performance: Fin size, # of stages, types of gates, etc. For optimal performance, we suggested using the NOR3 and for lowest power, the NAND2/NOR2 decoder is serviceable. We concluded that it was never worth using NAND3/INV because it consumed more power than NOR3 and could never outperform it.