Search this site

Embedded Files

Embedded Nexus

Home

Unlock your potential with Expert-led Embedded Systems Training and Hands-on projects!

Register Now

College Project

Home

Course-1 : Embedded System Master Class

Embedded System Master Class

Duration:

12 Weeks (3 months)

Course Structure:

1. Foundation (Weeks 1-3)

Week 1: Embedded Basics

Introduction to Embedded Systems
Microcontroller Architecture (ARM, AVR, etc.)
Basic Electronic Components (Sensors, Actuators)
Understanding Datasheets

Week 2: Programming Essentials

C for Embedded Systems
Bitwise Operations and Pointers
Writing and Debugging Bare-Metal Code
Practice: LED Blinking and GPIO Control

Week 3: Tools and Environment

IDE Setup (Keil, STM32CubeIDE, IAR)
Version Control with Git
Debugging with JTAG and Serial Monitors
Practice: Debugging a Simple Code

2. Application (Weeks 4-6)

Week 4: Peripheral Communication

UART, SPI, and I2C Protocols
Hands-on: UART-Based Serial Communication
Hands-on: SPI/I2C Sensor Interfacing

Week 5: ADC and PWM

Analog-to-Digital Conversion
Pulse Width Modulation for Motor Control
Hands-on: Reading ADC Values and Controlling LED Brightness

Week 6: Real-Time Systems

Basics of Real-Time Operating Systems (RTOS)
Task Scheduling and Prioritization
Hands-on: RTOS Implementation for Multi-Tasking

3. Optimization (Weeks 7-8)

Week 7: Memory Management

Flash and RAM Optimization
Stack and Heap Concepts
Debugging Memory Leaks

Week 8: Power Optimization

Low Power Modes in Microcontrollers
Energy-Efficient Code Design
Hands-on: Implementing Sleep Modes

4. Innovation (Weeks 9-10)

Week 9: Advanced Protocols

CAN, Ethernet, and Wireless Communication Basics
Hands-on: Implementing CAN/Ethernet Communication

Week 10: System Integration

Combining Multiple Peripherals
Debugging and Resolving Conflicts in Complex Systems
Hands-on: Building a Mini IoT Project

5. Growth (Weeks 11-12)

Week 11: Industry Standards and Best Practices

Embedded Coding Guidelines (MISRA C)
Writing Clean and Maintainable Code
Documentation and Testing

Week 12: Career Guidance and Final Project

Preparing for Embedded Job Interviews
Resume and Portfolio Building
Final Project Presentation (e.g., Robotic Arm, Data Logger, IoT Device)

Course-2 : Fundamentals of VLSI Design

Fundamentals of VLSI Design

Pricing (INR/USD) : ₹12,000 ($150)

Mode: Online/Offline

Prerequisites: Basic knowledge of electronics and digital logic

Duration:

6 Weeks (1.5 months) for Beginner

Course Structure:

Week 1: Introduction to VLSI & CMOS Technology

Evolution of VLSI and Moore’s Law
VLSI Design Flow & Methodologies
Overview of CMOS Technology
Fabrication Process of CMOS (PN Junctions, Oxidation, Etching, Doping)
CMOS Inverter: Working Principle

Week 2: Digital Logic & CMOS Circuits

Logic Gates using CMOS
Combinational vs Sequential Circuits
Pass Transistor & Transmission Gate Logic
Static & Dynamic Logic Circuits
Power Dissipation in CMOS Circuits

Week 3: Layout Design & Fabrication Process

Design Rules (Lambda-based & Micron Rules)
Layout Design of Basic Logic Gates
Stick Diagrams & Mask Layout
Design Rule Check (DRC), Layout vs Schematic (LVS)
Fabrication Process (Wafer Processing, Lithography, Deposition)

Week 4: VLSI Design Flow & Tools

RTL to GDSII Flow Overview
Introduction to HDL (Verilog/VHDL)
Logic Synthesis & Gate-Level Netlist
Static Timing Analysis (STA) Basics
Hands-on: Basic Verilog/VHDL Coding for Logic Gates

Week 5: Timing Analysis & Low Power Design

Timing Constraints in VLSI Design
Setup and Hold Time, Clock Skew
Introduction to Power Optimization Techniques
Clock Gating, Power Gating, Multi-Vt Design
Hands-on: Simulating Logic Circuits

Week 6: Testing, Packaging & Career Guidance

VLSI Testing & Fault Modeling
Design for Testability (DFT) Basics
Chip Packaging & Interconnects
Career Opportunities in VLSI (ASIC, FPGA, Physical Design, Verification)
Final Project: Designing a Simple Logic Block in Verilog

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Exercises with EDA Tools
✅ Mini-Project & Industry-Based Assignments
✅ Certification Upon Completion

Course-3 : ASIC Design and Verification

ASIC Design and Verification

Pricing (INR/USD) : ₹25,000 ($300)

Mode: Online/Offline

Prerequisites: Basics of Digital Logic, CMOS Circuits, and Verilog/VHDL

Duration:

08 Weeks (2 months) for Advanced

Course Structure:

Week 1: Introduction to ASIC Design

Introduction to ASIC, FPGA, and SoC
ASIC Design Flow (RTL to GDSII)
ASIC vs FPGA: Differences and Trade-offs
CMOS Fundamentals in ASIC Design
Overview of EDA Tools Used in ASIC Flow

Week 2: RTL Design & Verilog/VHDL Basics

RTL Design Fundamentals
Verilog & VHDL Coding Styles
Blocking vs Non-Blocking Assignments
FSM (Finite State Machine) Design in RTL
Hands-on: Simple RTL Design and Simulation

Week 3: Logic Synthesis & Static Timing Analysis (STA)

Logic Synthesis Flow & Constraints
Combinational & Sequential Timing Concepts
Setup Time, Hold Time, and Clock Skew
Introduction to Static Timing Analysis (STA)
Hands-on: Synthesizing a Design using EDA Tools

Week 4: ASIC Verification Fundamentals

Introduction to Functional Verification
Testbench Architecture & Verification Flow
Directed Testing vs Constrained Random Testing
Assertion-Based Verification (ABV) Basics
Hands-on: Writing Testbenches for RTL Designs

Week 5: SystemVerilog for Verification & UVM Basics

SystemVerilog Data Types, Interfaces, and OOP
Coverage-Driven Verification (Functional & Code Coverage)
Introduction to Universal Verification Methodology (UVM)
Hands-on: Implementing a Simple UVM Testbench

Week 6: DFT and Scan Chain Implementation

Introduction to Design for Testability (DFT)
Scan Chain, ATPG, and BIST Concepts
JTAG & Boundary Scan Testing
Hands-on: Implementing DFT Techniques in RTL

Week 7: ASIC Backend Flow & Physical Design Basics

Floorplanning, Placement, and Routing
Power Planning and Clock Tree Synthesis (CTS)
Parasitic Extraction & Timing Closure
Hands-on: Basics of Physical Design Using EDA Tools

Week 8: Final Project & Career Guidance

ASIC Tapeout Process Overview
Industry Standards and Best Practices
Final Project: End-to-End ASIC Design & Verification
Career Paths in ASIC Design (Front-end, Back-end, Verification)
Resume Building & Interview Preparation for ASIC Roles

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs using Industry Standard EDA Tools (Cadence/Synopsys/Mentor)
✅ Mini-Project & ASIC Verification Assignments
✅ Certification Upon Completion

Course-4 : FPGA Design and Development

FPGA Design and Development

Pricing (INR/USD) : ₹18,000 ($220)

Mode: Online/Offline
Prerequisites: Basics of Digital Logic, Verilog/VHDL, and Electronics

Duration:

06 Weeks (1.5 months) for Intermediate

Course Structure:

Week 1: Introduction to FPGA and Digital Design

Overview of FPGA vs ASIC vs Microcontroller
FPGA Architecture (LUTs, Flip-Flops, BRAM, DSP Blocks)
FPGA Vendors (Xilinx, Intel, Lattice, Microsemi)
HDL Introduction (Verilog/VHDL) for FPGA Design
Hands-on: Basic Logic Design using HDL

Week 2: FPGA Design Flow & Synthesis

FPGA Design Flow: RTL → Synthesis → Implementation → Bitstream
Hardware Description Languages (HDL) Best Practices
FPGA Development Tools (Vivado, Quartus, Libero)
Hands-on: Writing and Synthesizing Basic RTL Designs

Week 3: Timing Analysis and Constraints

FPGA Timing Concepts (Setup/Hold, Clock Skew, Jitter)
Static Timing Analysis (STA) in FPGA Design
Clocking Resources in FPGA (PLL, MMCM, Global Clocks)
Hands-on: Applying Timing Constraints in FPGA Design

Week 4: Simulation, Debugging, and IP Cores

Behavioral vs Post-Synthesis Simulation
Debugging with SignalTap (Intel) and Chipscope (Xilinx)
Introduction to IP Cores (Memory, DSP, UART, PCIe, Ethernet)
Hands-on: Using IP Cores in FPGA Designs

Week 5: FPGA-based System Design (AXI, SoC, Embedded Systems)

Interfacing Processors with FPGA (MicroBlaze, Nios II, ARM)
AXI Protocol & Bus Interfacing in FPGA
FPGA for Embedded Systems (Soft Processors & SoC Design)
Hands-on: Implementing a Soft Processor on FPGA

Week 6: Final Project & Career Guidance

Design Optimization Techniques (Power, Area, Speed)
FPGA Applications in AI, IoT, and Industrial Automation
Final Project: Implementing a Real-World FPGA Application
Career Paths in FPGA Design (RTL Design, Verification, Embedded FPGA)
Resume Building & Interview Preparation for FPGA Jobs

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs using FPGA Boards & EDA Tools (Vivado, Quartus, Libero)
✅ Mini-Project & Industry-Based Assignments
✅ Certification Upon Completion

Course-5 : VLSI Physical Design Flow

VLSI Physical Design Flow

Pricing (INR/USD) : ₹30,000 ($375)

Mode: Online/Offline
Prerequisites: Basics of Digital Logic, CMOS, Verilog/VHDL, and ASIC Design

Duration:

10 Weeks (2.5 months) for Advanced

Course Structure:

Week 1: Introduction to VLSI Physical Design

Overview of ASIC Design vs Physical Design
VLSI Design Flow (Front-End vs Back-End)
Introduction to CMOS Technology & Fabrication Process
Foundry Process Nodes (180nm to 3nm)
EDA Tools Used in Physical Design (Cadence, Synopsys, Mentor)

Week 2: Netlist to Layout Flow & Floorplanning

Netlist Preparation & Library Files (LEF, DEF, GDSII)
Floorplanning Concepts: Core Area, Die Size, Aspect Ratio
Macro Placement, I/O Planning, Power Planning
Hands-on: Floorplanning Using Cadence Innovus / Synopsys ICC2

Week 3: Placement and Optimization

Standard Cell Placement Techniques
Congestion Analysis & Optimization
Low Power Techniques in Placement (Multi-Vt, Power Gating)
Hands-on: Running Placement & Optimizing Congestion

Week 4: Clock Tree Synthesis (CTS)

Importance of Clock Tree in Timing Closure
Clock Skew, Jitter, and Buffer Insertion
CTS Algorithms (H-Tree, Balanced Tree, Mesh)
Hands-on: Implementing CTS Using Cadence/Synopsys

Week 5: Routing & Parasitic Extraction

Global Routing vs Detailed Routing
Metal Layers & Design Rule Constraints (DRC, LVS)
Signal Integrity Issues (Crosstalk, IR Drop, EM)
Parasitic Extraction & Delay Calculation (RC Extraction)
Hands-on: Running Routing & Parasitic Extraction

Week 6: Static Timing Analysis (STA) & Timing Closure

Setup/Hold Time Analysis & Slack Calculation
Multi-Mode Multi-Corner (MMMC) Analysis
Timing ECO (Engineering Change Order) Techniques
Hands-on: Performing STA & Timing Fixes in EDA Tools

Week 7: Power Analysis & Design for Manufacturability (DFM)

Power Estimation: Dynamic vs Leakage Power
IR Drop & Electromigration (EM) Analysis
Design for Manufacturability (DFM) & Yield Optimization
Hands-on: Running Power Analysis & DFM Checks

Week 8: Final Project & Career Guidance

Tapeout & Signoff Checks (DRC, LVS, ERC, ANT)
Final Project: End-to-End Physical Design of a Block
Career Opportunities in Physical Design (PD Engineer, STA Engineer)
Resume Building & Interview Preparation for VLSI Roles

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs using Industry Standard EDA Tools (Cadence Innovus, Synopsys ICC2, Mentor Calibre)
✅ Mini-Project & Physical Design Assignments
✅ Certification Upon Completion

Course-6 : Digital Design for VLSI Engineers

Digital Design for VLSI Engineers

Pricing (INR/USD) : ₹10,000 ($130)

Mode: Online/Offline
Prerequisites: Basic knowledge of Electronics & Boolean Logic

Duration:

05 Weeks (1.3 months) for Beginner

Course Structure:

Week 1: Introduction to Digital Logic & Number Systems

Overview of Digital vs Analog Systems
Number Systems: Binary, Octal, Hexadecimal
Boolean Algebra & Logic Gates
Logic Families: CMOS, TTL, ECL
Hands-on: Implementing Basic Logic Circuits

Week 2: Combinational Circuit Design

MUX, DEMUX, Encoder, Decoder, Adders, Subtractors
Parity Generators, Comparators, Multipliers
Design using K-Maps & Boolean Minimization
Hands-on: Combinational Circuit Simulation using HDL

Week 3: Sequential Circuit Design

Flip-Flops (SR, D, JK, T) & Latches
Counters (Synchronous & Asynchronous)
Shift Registers, FSM (Finite State Machine)
Hands-on: Designing FSMs for VLSI Applications

Week 4: RTL Design & Synchronous Design Concepts

Register Transfer Level (RTL) Design Basics
Synchronous vs Asynchronous Design
Clock Gating, Reset Strategies, Power Optimization
Hands-on: Writing RTL Code for Digital Circuits

Week 5: Timing Analysis & Optimization

Setup Time, Hold Time, Clock Skew, Jitter
Static Timing Analysis (STA) Basics
Pipelining & Retiming for Performance Optimization
Hands-on: Running Timing Analysis in EDA Tools

Week 6: Final Project & Industry Applications

Design of a Digital System (e.g., UART, ALU, Cache)
FPGA vs ASIC Implementation of Digital Circuits
Career Paths in Digital Design (RTL Engineer, FPGA Engineer)
Resume Building & Interview Preparation for VLSI Roles

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs using Verilog/VHDL in EDA Tools (Vivado, Quartus, ModelSim)
✅ Mini-Project & Digital Design Assignments
✅ Certification Upon Completion

Course-7 : RTL Design and Synthesis Using Verilog & VHDL

RTL Design and Synthesis Using Verilog & VHDL

Pricing (INR/USD) : ₹18,000 ($220)

Mode: Online/Offline
Prerequisites: Basics of Digital Logic and Electronics

Duration:

07 Weeks (1.7 months) for Intermediate

Course Structure:

Week 1: Introduction to RTL Design & HDLs

What is Register Transfer Level (RTL) Design?
ASIC vs FPGA-Based RTL Design
Overview of Hardware Description Languages (HDLs)
Verilog vs VHDL: Key Differences
Hands-on: Writing Basic Verilog & VHDL Code

Week 2: Verilog & VHDL Coding Fundamentals

Data Types, Operators, and Syntax
Combinational Logic Implementation
Blocking vs Non-Blocking Assignments (Verilog)
Processes, Signals, and Variables (VHDL)
Hands-on: Coding Basic Digital Circuits (MUX, Decoder, ALU)

Week 3: Sequential Logic & FSM Design

Flip-Flops, Counters, and Shift Registers
Finite State Machine (FSM) Design in Verilog & VHDL
Mealy vs Moore FSM Implementations
Hands-on: Designing a UART Controller Using FSM

Week 4: Synthesis & FPGA Implementation

Understanding RTL Synthesis Flow
Constraints & Optimization in Synthesis
FPGA Development Flow & Targeting FPGA Hardware
Hands-on: Synthesizing a Design in Xilinx Vivado/Intel Quartus

Week 5: Verification & Simulation

Testbenches for Functional Verification
Simulation Tools (ModelSim, Questa, Vivado Simulator)
Waveform Analysis & Debugging Techniques
Hands-on: Writing & Running a Testbench for an ALU

Week 6: Final Project & Career Guidance

RTL Optimization Techniques (Pipelining, Power Optimization)
ASIC vs FPGA Synthesis Considerations
Final Project: Design & Implement a Real-World Digital System
Career Paths in RTL Design (ASIC/FPGA Engineer)
Resume Building & Interview Preparation for RTL Design Roles

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs using Verilog/VHDL in EDA Tools (Vivado, Quartus, ModelSim)
✅ Mini-Project & RTL Design Assignments
✅ Certification Upon Completion

Course-8 : VLSI Verification Using System Verilog & UVM

VLSI Verification Using System Verilog & UVM

Pricing (INR/USD) : ₹35,000 ($430)

Mode: Online/Offline
Prerequisites: Basic Digital Design, Verilog/VHDL, and RTL Concepts

Duration:

10 Weeks (2.5 months) for Advanced

Course Structure:

Week 1: Introduction to VLSI Verification

Need for Verification in VLSI Design
Functional Verification vs Formal Verification
Basics of SystemVerilog for Verification
Simulation Tools Overview (Questa, VCS, Xcelium)
Hands-on: Writing & Running a Simple SystemVerilog Testbench

Week 2: SystemVerilog Data Types & Procedural Constructs

SV Data Types: Packed & Unpacked Arrays, Queues, Associative Arrays
Procedural Blocks: always, initial, final
Tasks & Functions: Differences, Usage, and Return Types
Hands-on: Implementing SystemVerilog Constructs in Testbenches

Week 3: Object-Oriented Programming (OOP) in SystemVerilog

OOP Concepts: Classes, Objects, Inheritance, Polymorphism
Mailbox & Semaphore for Inter-process Communication
Hands-on: Creating Reusable SystemVerilog Classes

Week 4: Coverage-Driven Verification & Assertions

Functional vs Code Coverage
Covergroups & Coverpoints in SystemVerilog
SystemVerilog Assertions (SVA) Basics
Hands-on: Writing Covergroups & Assertions

Week 5: Universal Verification Methodology (UVM) - Part 1

Introduction to UVM & Its Advantages
UVM Testbench Architecture: Sequence, Driver, Monitor, Scoreboard
UVM Factory & Configuration Database
Hands-on: Creating a Simple UVM Testbench

Week 6: Universal Verification Methodology (UVM) - Part 2

UVM Sequences, Transactions, and Phases
UVM Reporting & Messaging
Hands-on: Writing & Running UVM Test Cases

Week 7: UVM Advanced Topics & Debugging Techniques

UVM Register Abstraction Layer (RAL)
Debugging with Waveforms & Logs
Hands-on: Implementing UVM RAL for a Sample Design

Week 8: Final Project & Career Guidance

Verification of a Real-World Design (AXI, UART, SPI, RISC-V Core)
Coverage Closure & Sign-off Criteria
Career Paths in Verification (DV Engineer, Formal Verification Engineer)
Resume Building & Interview Preparation

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs Using SystemVerilog & UVM in EDA Tools (Questa, VCS, Xcelium)
✅ Mini-Project & Verification Assignments
✅ Certification Upon Completion

Course-9 : Low Power VLSI Design Techniques

Low Power VLSI Design Techniques

Pricing (INR/USD) : ₹15,000 ($190)

Mode: Online/Offline
Prerequisites: Basic Digital Design, CMOS Fundamentals, and VLSI Design

Duration:

06 Weeks (1.5 months) for Intermediate

Course Structure:

Week 1: Introduction to Low Power Design

Importance of Low Power in Modern VLSI
Power Dissipation in CMOS Circuits (Dynamic & Static Power)
Power vs Performance vs Area (PPA) Trade-offs
Low Power Design Challenges in ASIC & FPGA
Hands-on: Power Estimation of a Simple Digital Circuit

Week 2: Power Dissipation Sources & Reduction Techniques

Dynamic Power Reduction: Clock Gating, Multi-VDD, DVFS
Static Power Reduction: Power Gating, Leakage Reduction
Techniques for Low Power RTL Design
Hands-on: Implementing Clock Gating & Power Gating in RTL

Week 3: Low Power Synthesis & Optimization Techniques

Power-Aware Synthesis in ASIC Design Flow
Multi-VT Design & Its Impact on Power
Activity-Driven Power Optimization
Hands-on: Low Power Synthesis Using Synopsys Design Compiler

Week 4: Power Management Techniques in Physical Design

Low Power Floorplanning & Placement
Multi-Voltage Design Implementation
IR Drop & EM Analysis for Power Integrity
Hands-on: Power Routing & Optimization in Physical Design Tools

Week 5: Power Estimation & Verification

Power Analysis at Different Design Stages (Pre-layout vs Post-layout)
Power Estimation Tools (PrimeTime PX, PowerArtist, Voltus)
Power-Aware Verification & Functional Testing
Hands-on: Running Power Analysis on a Sample Design

Week 6: Final Project & Industry Applications

Power Optimization for a Real-World Design (Processor, Memory, AI Accelerator)
Trade-offs Between Performance, Power, and Cost
Career Paths in Low Power VLSI (Design Engineer, Power Architect)
Resume Building & Interview Preparation

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs Using Industry-Standard EDA Tools (Synopsys, Cadence, Siemens)
✅ Mini-Project & Low Power Design Assignments
✅ Certification Upon Completion

Course-10 : CMOS VLSI Circuit Design

CMOS VLSI Circuit Design

Pricing (INR/USD) : ₹22,000 ($275)

Mode: Online/Offline
Prerequisites: Basic Electronics, Digital Logic, and Semiconductor Physics

Duration:

08 Weeks (2 months) for Intermediate

Course Structure:

Week 1: Introduction to CMOS Technology

Evolution of VLSI & Moore’s Law
Basics of MOSFET (Enhancement & Depletion Type)
CMOS Inverter: Operation & Characteristics
Fabrication Process of CMOS Circuits
Hands-on: CMOS Inverter Simulation in LTspice

Week 2: MOSFET Characteristics & Modeling

MOSFET I-V Characteristics
Threshold Voltage & Body Effect
MOSFET Scaling & Short Channel Effects
SPICE Modeling of MOS Transistors
Hands-on: MOSFET DC & AC Analysis Using SPICE

Week 3: CMOS Logic Gates & Combinational Circuits

CMOS NAND, NOR, XOR Gate Design
Static & Dynamic Power Dissipation in CMOS Circuits
Delay Analysis & Logical Effort
Hands-on: Design & Simulate a CMOS Logic Gate

Week 4: Sequential Circuits & Memory Design

Latches & Flip-Flops in CMOS
Dynamic Logic & Pass Transistor Logic
SRAM & DRAM Design Principles
Hands-on: Implementing a Flip-Flop & Memory Cell in SPICE

Week 5: CMOS Design Techniques & Layout Basics

Standard Cell Design Methodology
Stick Diagrams & Layout Design Rules (Lambda Rules)
Parasitic Effects & Interconnect Issues
Hands-on: Layout Design of CMOS Logic Circuits Using Cadence Virtuoso

Week 6: Power & Performance Optimization in CMOS Design

Low Power Design Techniques (Clock Gating, Multi-VDD)
Performance Optimization (Pipelining, Parallelism)
Trade-offs Between Power, Area, and Speed
Hands-on: Power Analysis & Optimization of a CMOS Circuit

Week 7: ASIC vs FPGA & Industry Applications

ASIC vs FPGA: When to Use What?
Process Nodes & Technology Scaling (FinFET, GAAFET)
CMOS in AI Chips, IoT Devices, and High-Performance Computing
Hands-on: Implementing a CMOS Digital System in FPGA

Week 8: Final Project & Career Guidance

Complete CMOS Digital Circuit Design (ALU, UART, or RISC-V Core)
Layout & Fabrication Considerations
Career Paths in VLSI Design (ASIC Engineer, Circuit Design Engineer)
Resume Building & Interview Preparation

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs Using SPICE, Cadence Virtuoso, Synopsys Tools
✅ Mini-Project & CMOS Design Assignments
✅ Certification Upon Completion

Course-11 : Advanced VLSI Design and Layout

Advanced VLSI Design and Layout

Pricing (INR/USD) : ₹30,000 ($375)

Mode: Online/Offline
Prerequisites: Basic CMOS Design, Digital Design, and VLSI Layout Basics

Duration:

10 Weeks (2.5 months) for Advanced

Course Structure:

Week 1: Overview of Advanced VLSI Design

Introduction to ASIC & SoC Design Flow
Importance of Layout in VLSI Design
Design Rules & Technology Scaling (FinFET, GAAFET)
Industry-Standard EDA Tools (Cadence Virtuoso, Synopsys IC Compiler)
Hands-on: Setting Up a VLSI Design Environment

Week 2: Advanced CMOS Circuit Design

Complex Combinational & Sequential Circuits
Logical Effort & Transistor Sizing
Circuit Optimization for Power, Performance, and Area (PPA)
Hands-on: Design & Simulation of a Complex CMOS Circuit

Week 3: Custom & Semi-Custom Layout Design

Full-Custom vs Semi-Custom Design Methodologies
Standard Cell Design & Layout Techniques
Parasitic Extraction & Layout-Dependent Effects (LDE)
Hands-on: Layout of a Standard Cell in Cadence Virtuoso

Week 4: Design Rule Checking (DRC) & Layout vs Schematic (LVS)

Importance of DRC, LVS, & PEX in Layout Verification
Handling DRC Violations & Optimization Techniques
Hands-on: Running DRC & LVS on a Layout Design

Week 5: Physical Design & Floorplanning

Floorplanning & Placement Strategies
Power Planning & IR Drop Analysis
Routing Techniques & Clock Tree Synthesis (CTS)
Hands-on: Implementing a Floorplan in Cadence Innovus or Synopsys ICC

Week 6: Timing Analysis & Sign-off Checks

Introduction to Static Timing Analysis (STA)
Multi-Corner, Multi-Mode (MCMM) Timing Analysis
Signal Integrity & Crosstalk Issues
Hands-on: Running STA in PrimeTime

Week 7: Advanced Topics in VLSI Design

FinFET & Beyond: Challenges in Advanced Nodes (7nm, 5nm, 3nm)
AI-Driven VLSI Design & Layout Automation
Reliability & Yield Enhancement Techniques
Hands-on: Advanced Layout Optimization Techniques

Week 8: Final Project & Industry Applications

Complete Design & Layout of a Digital Block (ALU, Memory, or Interface Circuit)
Sign-off & Final Verification Checks
Career Paths in Physical Design & Custom Layout
Resume Building & Interview Preparation

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs Using Cadence Virtuoso, Synopsys IC Compiler, Mentor Calibre
✅ Mini-Project & Advanced Layout Design Assignments
✅ Certification Upon Completion

Course-12 : Embedded Systems and VLSI Co-Design

Embedded Systems and VLSI Co-Design

Pricing (INR/USD) : ₹22,000 ($275)

Mode: Online/Offline
Prerequisites: Basic Embedded Systems, Digital Design, and VLSI Fundamentals

Duration:

08 Weeks (2 months) for Intermediate

Course Structure:

Week 1: Introduction to Embedded Systems & VLSI Co-Design

Fundamentals of Embedded Systems & VLSI
Embedded vs VLSI: Where They Intersect
Hardware/Software Co-Design Approach
Applications in Automotive, IoT, and AI
Hands-on: Setting Up an Embedded VLSI Development Environment

Week 2: Embedded Processor Architectures & VLSI Design

RISC vs CISC Architectures (ARM, RISC-V)
Microcontrollers vs FPGAs vs ASICs
System-on-Chip (SoC) Architectures & Integration
Hands-on: Implementing a Simple Processor in Verilog/VHDL

Week 3: Memory Architectures & Optimization

SRAM, DRAM, Flash: Memory Selection for Embedded Systems
Memory Hierarchy & Cache Design in VLSI
Low-Power Memory Design Techniques
Hands-on: Memory Access Optimization in Embedded Code

Week 4: Hardware/Software Partitioning & Co-Simulation

Partitioning Logic Between Hardware & Software
FPGA-Based Embedded System Design
Co-Simulation Using ModelSim & SystemC
Hands-on: Running Co-Simulation for an Embedded Design

Week 5: Low-Power Design Techniques in Embedded & VLSI Systems

Dynamic Voltage & Frequency Scaling (DVFS)
Clock Gating & Power Gating in SoCs
Energy-Efficient Embedded System Design
Hands-on: Implementing Low-Power Strategies in an FPGA-Based Embedded System

Week 6: Interface & Communication Protocols

UART, SPI, I2C, CAN, and PCIe in Embedded-VLSI Systems
On-Chip Bus Architectures (AHB, AXI, Wishbone)
High-Speed Interfaces & Their Design Challenges
Hands-on: Verilog Implementation of an AXI-Based Communication Interface

Week 7: Real-Time Operating Systems (RTOS) & Embedded VLSI Applications

RTOS Concepts & Scheduling Techniques
Integration of RTOS with Custom Hardware
FPGA-Based AI & DSP Applications
Hands-on: Running RTOS on an FPGA-Based SoC

Week 8: Final Project & Industry Applications

Full Embedded-VLSI Co-Design Project (IoT Device, AI Accelerator, or Sensor Interface)
Industry Trends: Edge AI, Automotive VLSI, and Security in Embedded-VLSI Systems
Resume Building & Interview Preparation for Embedded & VLSI Jobs

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs Using ARM Cortex, FPGA Boards, Cadence, Synopsys Tools
✅ Mini-Project & Embedded-VLSI Design Assignments
✅ Certification Upon Completion

Course-13 : VLSI Testing and Fault Tolerance

VLSI Testing and Fault Tolerance

Pricing (INR/USD) : ₹18,000 ($220)

Mode: Online/Offline
Prerequisites: Digital Logic Design, VLSI Basics, Verilog/VHDL

Duration:

06 Weeks (1.5 months) for Intermediate

Course Structure:

Week 1: Introduction to VLSI Testing and Fault Tolerance

Importance of Testing in VLSI
Yield and Reliability Considerations
Common Faults in VLSI Circuits (Stuck-at, Bridging, Delay, etc.)
Fault Models and Their Applications
Hands-on: Simulating Basic Faults in a Digital Circuit

Week 2: Fault Modeling and Simulation

Stuck-at Fault Model (SAF)
Bridging Faults and Delay Faults
Fault Equivalence and Fault Collapsing
Hands-on: Implementing Fault Models in EDA Tools

Week 3: Testability Analysis and Design for Testability (DFT)

Controllability and Observability Concepts
Scan Chain Insertion (Full Scan, Partial Scan)
Built-In Self-Test (BIST) Techniques
Hands-on: Implementing Scan Chains in a Digital Design

Week 4: Automatic Test Pattern Generation (ATPG)

Introduction to ATPG Algorithms (D-Algorithm, PODEM, FAN)
Deterministic vs Random Test Pattern Generation
Fault Coverage and Test Set Optimization
Hands-on: Using ATPG Tools for Test Pattern Generation

Week 5: Memory Testing and Fault Tolerance

SRAM & DRAM Fault Models
March Tests and BIST for Memories
Error Detection and Correction (ECC, Hamming Codes)
Hands-on: Implementing BIST for Memory Testing

Week 6: Delay Testing and Scan-Based Testing

Path Delay and Transition Fault Testing
Scan-Based Timing Testing
Handling Process Variations in Delay Testing
Hands-on: Delay Test Implementation Using Synopsys/Cadence Tools

Week 7: Fault Tolerance in VLSI Systems

Redundancy Techniques (Triple Modular Redundancy, Error Recovery)
Fault-Tolerant Design in Processors and SoCs
Soft Errors and Radiation Effects in VLSI
Hands-on: Implementing Redundancy Techniques in FPGA-Based Design

Week 8: Final Project & Industry Applications

End-to-End Testing and Fault Tolerance for a Custom Digital Circuit
Industry Trends in VLSI Testing & Fault Tolerance
Resume Building & Interview Preparation for DFT and Testing Roles

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs Using Synopsys Tetramax, Cadence Modus, Mentor Tessent
✅ Mini-Project & Testing Assignments
✅ Certification Upon Completion

Course-14 : Custom IC Design Using Cadence Tools

Custom IC Design Using Cadence Tools

Pricing (INR/USD) : ₹30,000 ($375)

Mode: Online/Offline
Prerequisites: CMOS VLSI Design, Digital & Analog Circuit Design

Duration:

08 Weeks (2 months) for Advanced

Course Structure:

Week 1: Introduction to Custom IC Design and Cadence Environment

Overview of Custom IC Design vs Standard Cell Design
Introduction to Cadence Virtuoso, Spectre, and Layout XL
CMOS Device Physics and Design Rules
Hands-on: Setting Up Cadence Virtuoso and Creating a Simple Schematic

Week 2: Schematic Design and Circuit Simulation

Understanding MOSFET Characteristics in Virtuoso
Creating Custom Analog and Digital Circuit Schematics
SPICE-Based Circuit Simulation using Spectre
Hands-on: Design and Simulation of an Inverter & NAND Gate

Week 3: Layout Design and Design Rule Check (DRC)

Layout Techniques for Performance and Reliability
Design Rule Constraints (Width, Spacing, Alignment)
Introduction to DRC (Design Rule Check) Using Assura/Calibre
Hands-on: Layout Design of a CMOS Inverter & Running DRC

Week 4: Parasitic Extraction and Layout vs Schematic (LVS) Check

Understanding Parasitic Effects in Custom IC Design
Introduction to Layout vs Schematic (LVS) Check
Parasitic Extraction with Quantus/XRC
Hands-on: Running LVS and Fixing Layout Errors

Week 5: Analog Custom IC Design & Simulation

Operational Amplifier (Op-Amp) Design in Virtuoso
Current Mirrors and Differential Pair Design
AC, DC, and Transient Analysis in Spectre
Hands-on: Designing and Simulating a Two-Stage Op-Amp

Week 6: Performance Optimization and Post-Layout Simulation

Sizing and Biasing Optimization for Performance
Post-Layout Simulation and Parasitic Effects Analysis
Noise Analysis and Monte Carlo Simulations
Hands-on: Optimizing an Op-Amp for High Gain and Low Noise

Week 7: Mixed-Signal IC Design (Custom Analog + Digital Blocks)

Overview of Mixed-Signal Design in Cadence
Integrating Analog and Digital Components
Custom PLL and ADC Design Basics
Hands-on: Designing a Simple ADC Block with Custom Analog and Digital Sections

Week 8: Final Project & Industry Applications

Full-Custom Design Project (Analog, Digital, or Mixed-Signal Circuit)
Overview of Tape-Out Process and Industry Standards
Resume Building & Interview Preparation for Custom IC Design Roles

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs Using Cadence Virtuoso, Spectre, Assura, Quantus
✅ Mini-Project & Custom IC Layout Assignments
✅ Certification Upon Completion

Course-15 : SoC (System on Chip) Design and Verification

SoC (System on Chip) Design and Verification

Pricing (INR/USD) : ₹35,000 ($430)

Mode: Online/Offline
Prerequisites: Digital Design, RTL Coding (Verilog/VHDL), Basic VLSI & FPGA Concepts

Duration:

10 Weeks (2.5 months) for Advanced

Course Structure:

Week 1: Introduction to SoC Design and Architecture

What is an SoC? Components & Challenges
SoC vs ASIC vs FPGA vs Microcontroller
Hardware-Software Co-Design Basics
Hands-on: SoC Architecture Overview Using ARM-based Platforms

Week 2: IP-Based SoC Design and Integration

IP Cores and Reuse Methodologies
Bus Interfaces (AXI, AHB, APB, Wishbone)
IP Wrapping and Integration in SoC
Hands-on: Connecting an IP Core in a SoC Design

Week 3: RTL Design and Synthesis for SoC Components

Writing Efficient RTL for SoC Components
High-Level Synthesis (HLS) for SoC
Synthesis Process & Timing Constraints
Hands-on: Synthesizing a Processor Core for SoC

Week 4: Verification of SoC Components (Block-Level Verification)

Functional Verification Basics
Testbenches for SoC Components
Code Coverage & Functional Coverage
Hands-on: Writing a SystemVerilog Testbench for an SoC Block

Week 5: SoC Level Verification (Integration Testing)

SoC Verification Plan & Test Strategy
UVM-Based Verification for SoC
Debugging and Waveform Analysis
Hands-on: Running a UVM-Based SoC Testbench

Week 6: FPGA Prototyping and Emulation of SoC

Why FPGA Prototyping for SoC?
Mapping SoC RTL to FPGA
Hardware-Software Co-Simulation
Hands-on: Running an SoC Design on an FPGA Board

Week 7: Low-Power and Performance Optimization for SoC

Power Domains and Clock Gating in SoC
DVFS (Dynamic Voltage and Frequency Scaling)
Performance Bottlenecks in SoC Design
Hands-on: Implementing Power Optimization in SoC

Week 8: Final Project & Industry Applications

Design and Verification of a Mini SoC (Processor + Peripherals)
Industry Trends in SoC Development
Resume Building & Interview Preparation for SoC Design and Verification

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs Using Cadence/Xilinx/Vivado/QEMU
✅ Mini-Project & SoC Verification Assignments
✅ Certification Upon Completion

Course-16 : VLSI for AI and Machine Learning Applications

VLSI for AI and Machine Learning Applications

Pricing (INR/USD) : ₹28,000 ($350)

Mode: Online/Offline
Prerequisites: Digital Design, RTL Coding (Verilog/VHDL), FPGA Basics, Machine Learning Fundamentals

Duration:

08 Weeks (2 months) for Advanced

Course Structure:

Week 1: Introduction to AI Hardware and VLSI for ML

Evolution of AI Hardware and Role of VLSI
Key AI Workloads: CNNs, RNNs, Transformers, Edge AI
Overview of AI Accelerators: TPU, GPU, NPU, FPGAs, Custom ASICs
Hands-on: Setting Up a Neural Network for Hardware Acceleration

Week 2: Digital Design for AI Accelerators

Fixed-Point vs Floating-Point Arithmetic in AI Hardware
MAC (Multiply-Accumulate) Units and Matrix Computations
High-Throughput vs Low-Power Design Trade-offs
Hands-on: RTL Implementation of a MAC Unit

Week 3: FPGA-Based AI Acceleration

Why FPGA for AI? Benefits and Challenges
AI Model Deployment on FPGA (Xilinx/Vivado, Intel Quartus)
Introduction to High-Level Synthesis (HLS) for AI Workloads
Hands-on: Running a Neural Network on an FPGA Board

Week 4: ASIC Design for AI Processing Units

ASIC Design Flow for AI Processors
Design Considerations: Memory Bandwidth, Latency, Power
Case Study: Google TPU & NVIDIA DLA (Deep Learning Accelerator)
Hands-on: Implementing a Small AI Accelerator in RTL

Week 5: Low-Power and Energy-Efficient AI Hardware

Low-Power Techniques: Approximate Computing, Clock Gating, DVFS
Memory Hierarchy Optimization for AI Workloads
Neuromorphic Computing and Spiking Neural Networks
Hands-on: Power Optimization of an AI Accelerator

Week 6: Edge AI and TinyML with VLSI

Introduction to Edge AI and TinyML
Hardware Constraints: Power, Latency, Cost
AI Hardware for IoT and Embedded Systems
Hands-on: Deploying a TinyML Model on an Embedded FPGA

Week 7: Custom AI Chip Design and Verification

Chip Architecture for AI Workloads
Design Verification Challenges for AI Chips
AI Accelerator Testing & Debugging Strategies
Hands-on: UVM-Based Verification of a MAC Array

Week 8: Final Project & Industry Applications

Design and Implementation of an AI Processing Unit
Industry Trends: AI Hardware Startups & Research
Resume Building & AI Chip Design Interview Preparation

Course Deliverables:

✅ Lecture Notes & Recorded Sessions
✅ Hands-on Labs Using Cadence/Xilinx/Intel/FPGA
✅ Mini-Project & AI Accelerator Design Assignments
✅ Certification Upon Completion

Why Choose Us?

Expert Trainer
Hands-On Projects
Comprehensive Curriculum
Job Ready Skills
Certified Training
Affordable Fees
Personalized Support
Flexible Learning
Professional Network
Proven Results

What You’ll Gain ?

Technical Skills
Industry Knowledge
Project Experience
Job Readiness
Problem-Solving
Hands-On Practice
Certification
Confidence
Community Support
Career Growth

Who I'M ?

I’m Krishna Kapoor, an embedded systems professional with over 6 years of experience. specialize in microcontroller programming, sensor integration, and real-world project development. Through my coaching business, Embedded Nexus, I aim to empower individuals with the skills they need to succeed in the embedded systems industry.

Benefits

Expert Guidance: Learn directly from an experienced embedded systems professional.
Practical Projects: Gain hands-on experience with real-world applications.
Job-Ready Skills: Master industry-relevant protocols like I2C and SPI, UART, USART, USB, EATHERNET, CAN, RS422/232 etc.
Recognized Certification: Showcase your expertise with a valued certificate.
24/7 Support: Access personalized mentorship and resources anytime.

Bonus Resources:

Weekly Assignments
Doubt-Clearing Live Sessions
Certification of Completion

Smriti Shree

Director of

Embedded Nexus

Krishna Kapoor

CEO & Founder of Embedded Nexus

Ladli Singh

Assistance Director (AD) of Embedded Nexus

EMBEDDED NEXUS

"Innovate. Integrate. Excel."

Disclaimer: All trademarks, logos and brand names are the property of their respective owners. All company, product and service names used in this website are for identification purposes only. Use of these names, trademarks and brands does not imply endorsement.

Google Sites

Report abuse

Page details

Page updated

Google Sites

Report abuse