Publications

International Journal

[10] Yaebin Moon, Wanju Doh, Kwanhee Kyung, Eojin Lee, and Jung Ho Ahn, "ADT: Aggressive Demotion and Promotion for Tiered Memeory," IEEE Computer Architecture Letters (CAL), 2023.

[9] Sungmin Yun, Byeongho Kim, Jaehyun Park, Hwayong Nam, Jung Ho Ahn, and Eojin Lee, "GraNDe: Near-Data Processing Architecture with Adaptive Matrix Mapping for Graph Convolutional Networks," IEEE Computer Architecture Letters (CAL), 2022. (also selected as a presenting paper at the Best of CAL session at HPCA 2023)

[8] Deok-Jae Oh, Yaebin Moon, Do Kyu Ham, Tae Jun Ham, Yongjun Park, Jae W Lee, Jung Ho Ahn, and Eojin Lee, "MaPHeA: A Framework for Lightweight Memory Hierarchy-Aware Profile-Guided Heap Allocation," ACM Transactions on Embedded Computing Systems (TECS), 2022.

[7] Wonkyung Jung, Eojin Lee, Sangpyo Kim, Jongmin Kim, Namhoon Kim, Keewoo Lee, Chohong Min, Jung Hee Cheon, and Jung Ho Ahn, "Accelerating Fully Homomorphic Encryption Through Architecture-centric Analysis and Optimization," IEEE Access, 2021.

[6] Byeongho Kim, Jaehyun Park, Eojin Lee, Minsoo Rhu, and Jung Ho Ahn, "TRiM: Tensor Reduction in Memory," IEEE Computer Architecture Letters (CAL), 2021.

[5] Byeongho Kim, Jongwook Chung, Eojin Lee, Wonkyung Jung, Sunjung Lee, Jaewan Choi, Jaehyun Park, Minbok Wi, Sukhan Lee, and Jung Ho Ahn, "MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks," IEEE Transactions on Computers (TC), 2020.

[4] Ingab Kang, Eojin Lee, and Jung Ho Ahn, "CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention," IEEE Access, 2020.

[3] Yuhwan Ro, Eojin Lee, and Jung Ho Ahn, "Evaluating the Impact of Optical Interconnects on a Multi-Chip Machine-Learning Architecture," MDPI Electronics, 2018.

[2] Eojin Lee, Sukhan Lee, G. Edward Suh, and Jung Ho Ahn, "TWiCe: Time Window Counter Based Row Refresh to Prevent Row-Hammering," IEEE Computer Architecture Letters (CAL), 2018.

[1] Yuhwan Ro, Eojin Lee, and Jung Ho Ahn, "Reset-in-Set: Improving PCM Write Throughput by Reducing the Peak Power of Multi-bit Writes," Electronics Letters, 2015.

International Conference

[10] Minbok Wi, Jaehyun Park, Seoyoung Ko, Nam Sung Kim, Eojin Lee, and Jung Ho Ahn, "SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling," in Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA), February, 2023 (to appear).

[9] Shinhaeng Kang, Sukhan Lee, Byeongho Kim, Hweesoo Kim, Kyomin Sohn, Nam Sung Kim, and Eojin Lee, "An FPGA-based RNN-T Inference Accelerator with PIM-HBM," in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), February, 2022.

[8] Jaehyun Park, Byeongho Kim, Sungmin Yun, Eojin Lee, Minsoo Rhu, and Jung Ho Ahn, "TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory," in Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO), October, 2021.

[7] Deok-Jae Oh, Yaebin Moon, Eojin Lee, Tae Jun Ham, Yongjun Park, Jae W Lee, and Jung Ho Ahn, "MaPHeA: A Lightweight Memory Hierarchy-Aware Profile-Guided Heap Allocation Framework," in Proceedings of the ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), June 2021.

[6] Sukhan Lee, Shin-haeng Kang, Jaehoon Lee, Hyeonsu Kim, Eojin Lee, Seungwoo Seo, Hosang Yoon, Seungwon Lee, Kyounghwan Lim, Hyunsung Shin, Jinhyun Kim, Seongil O, Anand Iyer, David Wang, Kyomin Sohn, and Nam Sung Kim, "Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology," in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2021.

[5] Heesu Kim, Hanmin Park, Taehyun Kim, Kwanheum Cho, Eojin Lee, Soojung Ryu, Hyuk-Jae Lee, Kiyoung Choi, and Jinho Lee, "GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent," in Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2021.

[4] Yeonhong Park, Woosuk Kwon, Eojin Lee, Tae Jun Ham, Jung Ho Ahn, and Jae W Lee, "Graphene: Strong yet Lightweight Row Hammer Protection," in Proceedings of the IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2020.

[3] Eojin Lee, Ingab Kang, Sukhan Lee, G. Edward Suh, and Jung Ho Ahn, "TWiCe: Preventing Row-hammering by Exploiting Time Window Counters," in Proceedings of the IEEE/ACM International Symposium on Computer Architecture (ISCA), June 2019.

[2] Eojin Lee, Jongwook Chung, Daejin Jung, Sukhan Lee, Sheng Li, and Jung Ho Ahn, "Work as a Team or Individual: Characterizing the System-Level Impacts of Main Memory Partitioning," in Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), October 2017.

[1] Yuhwan Ro, Hyunyoon Cho, Eojin Lee, Daejin Jung, Young Hoon Son, Jung Ho Ahn, and Jae W Lee, "SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures," in Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA), February 2017.

Arxiv

[1] Wonkyung Jung, Eojin Lee, Sangpyo Kim, Keewoo Lee, Namhoon Kim, Chohong Min, Jung Hee Cheon, and Jung Ho Ahn, "HEAAN Demystified: Accelerating Fully Homomorphic Encryption Through Architecture-centric Analysis and Optimization," arXiv preprint arXiv:2003.04510, 2020.

Domestic Journal and Conference

[2] 강인갑, 이어진, 안정호, "SPEC CPU2017 벤치마크를 이용한 다단계 NUMA 시스템에서 메모리 접근 지연시간과 대역폭에 따른 성능 변화 연구", 대한전자공학회 추계학술대회, 2018.

[1] 강철호, 오덕재, 이어진, 안정호, "스토리지 기반 키-밸류 스토어를 이용한 대용량 DRAM/NVM 이종 메인 메모리 시스템의 유효성 검증", 대한전자공학회 하계종합학술대회, 2018.