This is the course website for EE375, "Computer Architecture with Microcontrollers", taught by MAJ Nathan Jones to a group of West Point Cadets during AY23-1 (Aug-Dec 2022). This course occurs directly after an introductory course on digital logic; see this lesson for more information about what material a student of this course is expected to know coming in to the course. The course objectives are listed below.
This course is offered in the style of a Modern Classroom, meaning nearly 100% of the course material (including lectures!) is available either online or in the course textbook. This allows students in EE375, and anyone else who comes across this website, to complete the course on their own and entirely at their own pace. You can start the course by opening up the menu and navigating to one of the course units. Happy hacking!
BUILD a computer,
WRITE software for that computer, and
COMPARE that computer to other computers.
Or, more specifically:
Describe and implement the control and datapath of a non-pipelined RISC CPU, including support for interrupts/exceptions and input/output
Describe the ISA of the CPU, including the register model, memory map, control registers, interrupt process, input/output, etc
Write assembly language programs for that RISC CPU which utilize interrupts and/or input/output
Debug assembly language programs using a simulator/debugger
Describe how the CPU facilitates/implements high-level language features and support for operating systems, including:
Procedure calling
Interrupts/exceptions
Input/output
Privileged modes
Compare microcontrollers with microprocessors; Pick a processor for a given project
Describe metrics of evaluation including speed, memory size/access times, power usage, peripherals, ease of development, etc
Describe speed enhancements including pipelining and caching
Identify some contributors to computer architecture and organization and relate their achievements to the knowledge area.
Describe what is meant by 'computer architecture' and discuss historical and future computer architecture trends.