EDFLOW21

Paper abstract

Event cameras such as the Dynamic Vision Sensor (DVS) are useful because of their low latency, sparse output, and high dynamic range.  This paper proposes a DVS+FPGA camera platform  and uses it to demonstrate  the hardware implementation of event-based corner keypoint detection and adaptive block-matching optical flow.  To adapt sample rate dynamically, events are accumulated in event slices using the area event count slice method.  The area event count is feedback controlled by the average optical flow matching distance. Corners are detected  by streaks of accumulated events on event slice rings of 1 and 2 pixels. Corner detection takes only 6 clock cycles (16 MHz event rate at the 100MHz clock frequency).  At the corners, flow vectors are computed in 100 clock cycles (1 MHz event rate). The multiscale block match size is 25x25 pixels and the flow vectors span up to 30-pixel match distance over the 3 matching scales.  The FPGA processes the sum-of-absolute distance block matching at 123 GOp/s, the equivalent of 1230 Op/clock cycle. EDFLOW is much more accurate  on MVSEC drone and driving optical flow benchmarking sequences than the previous best DVS FPGA optical flow implementation, and achieves similar accuracy to the CNN-based EV-Flownet,