Syllabus

Course Overview

• Digital design coding using advance SystemVerilog constructs
• Learn SystemVerilog through examples and project
  • Synthesis each design example and visualize circuit
• SystemVerilog Modeling styles
• Learn how to develop SystemVerilog testbench and perform RTL simulation
• SystemVerilog Synthesis Coding Guidelines through example
• Digital design timing and pipeling fundamentals
• Understand FPGA architecture and synthesis RTL code for FPGA
• ASIC and FPGA design flow
• Introduction to SystemVerilog Assertions
• Two quizzes, Assignments, Final projects and presentation
  • Assignments and projects includes designing of circuits, develop testbench, synthesis design using Altera Quartus, Simulate using Modelsim, review timing reports and debug waveforms. Includes documenting assignments and projects.
• EDA Tools :
  • Learn how to use modelsim simulator to perform RTL simulation and debug waveforms
  • Debugging waveforms using Novas Verdi
  • Learn how to use Altera Quartus FPGA tool sets to perform synthesis, view RTL and post mapping nelist and review timing reports

Books and References

• Primary Textbook :
  • RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design, 1st Edition
  • Author : Stuart Sutherland, ISBN-13: 978-1546776345 / ISBN-10: 1546776346
• Additional References :
  • Digital Design and Computer Architecture, Second Edition
  • Authors : David Harris and Sarah Harris , Morgan Kaufmann
  • ISBN-10: 0123944244; ISBN-13: 978-0123944245
  • Make sure you get the 2nd Edition since the 1st Edition uses Verilog instead of SystemVerilog.
• Books recommended, but NOT required.
• IEEE SystemVerilog LRM : https://standards.ieee.org/standard/1800-2012.html
• Accellera : https://www.accellera.org/downloads/standards

Grading Policy

• Quizzes : 20% of final grade
  • There are 2 pop-up quizzes during the quarter. They will not be announced beforehand so make sure you attend lectures.
• Assignments : 30% of final grade
  • There will be multiple programming-based assignments. For details on assignments and deadlines will be published on the schedule page.
• Final project and presentation : 45% of final grade
  • RTL code development, FPGA synthesis, Verification and Final Presentation
  • More information on the final project will be presented later in this quarter.
• Attendance : 5% of final grade
  • Download iclicker app or purchase the equipment from campus stores :
  • https://www.iclicker.com/students/

More information on the final project will be presented later in this quarter.

Late or Missed Assignments/Missed Exam Policy

You can submit assignments one day late for 10% late penalty.

Academic Integrity

In this course we expect students to adhere to the UC San Diego Integrity of Scholarship Policy. This means that you will complete your work honestly, with integrity, and support and environment of integrity within the class. Here are few examples of what is considered as reasonable and unreasonable collaboration.

Reasonable

• Discussing assignments and course material
• Using online resources to solve assignments, so long as they're not solutions to the assigned problems.

Unreasonable

• Viewing a classmate's solution in order to solve your assignment
• Giving your assignment solution to another student
• Looking at another student's quiz during exams
• Copying a previous course/project as your final project