Publications

Journal Papers 

1. Ko-Hong Lin, Ont-Derh Lin, Shi-Yu Huang and Duo Sheng, “Low-jitter frequency doubling circuit supporting higher-speed BISG and aging sensing in a chiplet-based design environment,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 12, pp. 2210-2219, Dec. 2024.

2. Duo Sheng, Hao-Ting Huang, Ruey-Lin Liu, Cheng-I Cheng and Xiao-Ti Wang, “A configurable resolution time-to-digital converter with low PVT sensitivity for LiDAR applications,” Electronics, vol. 13, Jul. 2024.

3.  Duo Sheng, Hsin-Ting Lee, and Fu-Chi Huang, “All-digital transmit beamformer for portable high-frequency ultrasound imaging systems,” Review of Scientific Instruments, vol. 94, Mar. 2023.

4. Duo Sheng, Hsueh-Ru Lin, and Li Tai, “Low-process–voltage–temperature-sensitivity multi-stage timing monitor for system-on-chip applications,” Electronics, vol. 10, Jun. 2021.

5. Duo Sheng, Wei-Yen Chen, Hao-Ting Huang, and Li Tai, “Digitally controlled oscillator with high timing resolution and low complexity for clock generation,” Sensors, vol. 21, Feb. 2021.

6. Ching-Che Chung, Duo Sheng, and Ming-Hsuan Li, “Design of a Human Body Channel Communication Transceiver Using Convolutional Codes,” Microelectronics Journal, vol. 100, Jun. 2020.

7. Duo Sheng, Sheng-Min Chan, Chun-Wei Lin, and Chih-Chung Huang, “32-Channel transmit beamformer with high timing resolution for high-frequency ultrasound imaging systems,” Review of Scientific Instruments, vol. 91, May 2020.

8. Duo Sheng, Jun-Wei Lin, Yi-Hsiang Wang, and Chih-Chung Huang, “High-Resolution all-digital transmit beamformer for high-frequency and wearable ultrasound imaging systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 2, pp. 492-502, Feb. 2020.

9. Duo Sheng, Chun-Wei Lin, Ying-Chen Shih, and Yun-An Yang, “Dual-cell structure digitally controlled oscillator with portability for clock generation applications,” Review of Scientific Instruments, vol. 90, May 2019.

10. Ching-Che Chung, Duo Sheng, Ming-Chieh Li, and Yi-Che Tsai, “A fast phase tracking reference-less all-digital CDR circuit for human body channel communications,” Microelectronics Journal, vol. 84, pp.97-95, Feb. 2019.

11. Duo Sheng and Yu-Chan Hung, “Wide-range and high-resolution on-chip delay measurement circuit with low supply-voltage sensitivity for SoC applications,” Review of Scientific Instruments, vol. 87, Nov. 2016.

12. Duo Sheng and Min-Rong Hong, “A low-power all-digital on-chip CMOS oscillator for a wireless sensor node,” Sensors, vol. 16, Oct. 2016.

13. Ching-Che Chung, Duo Sheng, and Chang-Jun Li, “A wide-range low-cost all-digital duty-cycle corrector,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 11, pp. 2487-2496, Nov. 2015.

14. Ching-Che Chung, Duo Sheng, and Wei-Da Ho, “A low-cost low-power all-digital spread-spectrum clock generator,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, pp. 983-987, May. 2015.

15. Duo Sheng, Hsiu-Fan Lai, Sheng-Min Chan and Min-Rong Hong, “A high resolution on-chip delay sensor with low supply-voltage sensitivity for high-performance electronic systems,” Sensors, vol. 15, pp. 4408-4424, Feb. 2015.

16. Ching-Che Chung, Duo Sheng, and Sung-En Shen, “High-resolution all-digital duty-cycle corrector in 65-nm CMOS technology,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1096-1105, May. 2014.

17. Duo Sheng, Ching-Che Chung, Hsiu-Fan Lai, and Shu-Syun Jhao, “High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications,” IEICE Electronics Express (ELEX), vol. 11, no. 3, Jan. 2014.

18. Duo Sheng, and Wei-Da Ho, “A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS,” IEICE Electronics Express (ELEX), vol. 10, no. 6, Mar. 2013.

19. Ching-Che Chung, Duo Sheng, and Ning-Mi Hsueh, “A high-performance wear-leveling algorithm for flash memory system,” IEICE Electronics Express (ELEX), vol. 9, no. 24, pp. 1874-1880, Dec. 2012.

20. Ching-Che Chung, Duo Sheng, Chia-Lin Chang, Wei-Da Ho, Yang-Di Lin, and Fang-Nien Lu, “An all-digital large-N audio frequency synthesizer for HDMI applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 7, pp. 424-428, Jul. 2012.

21. Duo Sheng, Ching-Che Chung, Jhih-Ci Lan, and Hsiu-Fan Lai, “Monotonic and low-power digitally controlled oscillator with portability for SoC applications,” Electronics Letters, vol. 48, no. 6, pp. 321-323, Mar. 2012.

22. Ching-Che Chung, Duo Sheng, and Sung-En Shen, “A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology,” IEICE Electronics Express (ELEX), vol. 8, no. 15, pp. 1245-1251, Aug. 2011.

23. Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 6, pp. 1113-1117, Jun. 2011.

24. Ching-Che Chung, Duo Sheng, and Chia-Lin Chang, “A 600 kHz to 1.2 GHz all-digital delay-locked loop in 65nm CMOS technology,” IEICE Electronics Express (ELEX), vol. 8, no. 7, pp. 518-524, Apr. 2011.

25. Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “Wide Duty Cycle Range Synchronous Mirror Delay Designs,” Electronics Letters, vol. 46, no.5, pp. 338-340, Mar. 2010.

26. Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “Fast-Lock All-Digital DLL and Digitally-Controlled Phase Shifter for DDR Controller Applications,” IEICE Electronics Express, vol. 7, no.9, pp. 634-639, May 2010.

27. Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 54, no. 11, pp. 954-958, Nov. 2007.

28. Jinn-Shyan Wang, Po-Hui Yang, and Duo Sheng, “Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops,” IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 583–592, Apr. 2000. 

Conference Papers 

1.  Duo Sheng and Yen-Ling Wang,“ Low-PVT-sensitive two-stage time-to-digital converter with time amplifier,” 7th International Conference on Circuits and Systems (ICCS), Sep. 2025.

2. Duo Sheng, Chao-Kai Pai, Yi-Ju Chen, Bo-An Chen, Hao-Yuan Cheng, Ke-Jhong Tan and Ri-En Yeh,“ An all-digital capacitance-to-digital converter based on time-to-digital converter,” 24th International Conference on Electronics, Information, and Communication (ICEIC 2025), Jan. 2025.

3. Duo Sheng, Ying-Chi Chiu, Yun-Quan Li, You-Ning Lo, Chao-Kai Pai, and Ten-Ling Wang, “A digital receive beamforming IC for high-frequency ultrasound imaging system,” IEEE International Conference on ASIC (ASICON), Oct. 2023.

4. Duo Sheng, Duo Sheng, Chih-Hao Liu, Sih-Ying Chen, Bin-Yang Song, Ying-Chi Chiu, and Ming-Han Cai, “DLL-based transmit beamforming IC for high-frequency ultrasound medical imaging system,” IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), Sep. 2021.

5. Duo Sheng, Wei-Yen Chen, Yu-Hsiang Chang, and Hao-Ting Huang, “High-timing-resolution and low-complexity cell-based digitally controlled oscillator,” IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), Sep. 2020.

6. Duo Sheng, Chia-Lin Wu, Yu-Chan Hung, and Yi-Shang Wang, “All-digital and low-power reference clock generator for biotelemetry applications,” International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Jul. 2016.

7. Duo Sheng, Chih-Chung Huang, Zong-Ru Yang, and Yi-Shang Wang, “An all-digital and high-resolution transmit beamforming ASIC for high-frequency and portable ultrasonic imaging systems,” IEEE International Ultrasonics Symposium (IUS), Oct. 2015. 

8. Duo Sheng, Ching-Che Chung, Chia-Lin Wu, Sheng-Min Chan, and Min-Rong Hong, “An all-digital and wide-range reference clock generator for biotelemetry applications,” International Conference on Electronics and Software Science (ICESS), Jul. 2015.

9. Ching-Che Chung, Duo Sheng, and Chen-Han Chen, “An all-digital phase-locked loop compiler with liberty timing files,” International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2014.

10. Duo Sheng, Ching-Che Chung, Chih-Chung Huang, and Jia-Wei Jian, “A high-resolution and one-cycle conversion time-to-digital converter architecture for PET image applications,” International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Jul. 2013.

11. Duo Sheng, Ching-Che Chung, and Jhih-Ci Lan, “A monotonic and low-power digitally controlled oscillator using standard cells for SoC applications,” IEEE 4th Asia Symposium on Quality Electronic Design (ASQED), Jul. 2012.

12. Ching-Che Chung, Duo Sheng, and Yang-Di Lin, “An all-digital clock and data recovery circuit for spread spectrum clocking applications in 65nm CMOS technology,” IEEE 4thAsia Symposium on Quality Electronic Design (ASQED), Jul. 2012.

13. Ching-Che Chung, Duo Sheng, and Wei-Da Ho, “A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology,” International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2012.

14. Duo Sheng, and Jhih-Ci Lan, “A monotonic and low-power digitally controlled oscillator with portability for SoC applications,” 54th IEEE Midwest Symposium on Circuits and Systems, Aug. 2011.

15. Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “An all digital spread spectrum clock generator with programmable spread ratio for SoC applications,” IEEE Asia Pacific Conf. on Circuits and Systems, Nov. 2008,.

16. Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “An all-digital phase-locked loop with high-resolution for SoC applications,” International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2006.

17. Duo Sheng, Ching-Che Chung, and Chen-Yi Lee, “A fast-lock-in ADPLL with high-resolution and low-power DCO for SoC applications,” IEEE Asia Pacific Conf. on Circuits and Systems, Dec. 2006.

18. Jinn-Shyan Wang, Pei-Lung Lin, Wern-Ho Sheen, Duo Sheng, and Yu-Ming Huang, “A compact adaptive equalizer IC for HIPERLAN system,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2000. 

Patents 

• US Patents

1. Duo Sheng, Min Nan Yen, Ken Liou, “Re-programmable logic array,” US Patent No. 6693453, 2004.

2. Min Nan Yen and Duo Sheng, “Memory device having built-in error-correction capabilities,” US Patent No. 7079430, 2006.

3. Min Nan Yen, Duo Sheng, Shou-Chang Tsai, Koug Mou Liou, “Digital phase-locked loop compiler,” US Patent No. 7145975, 2006. 

• R.O.C Patents

1.  嚴敏男，盛鐸，“具有內建錯誤糾正能力之記憶體元件”，中華民國專利發明第 I301975 號，民國97年。

2. 嚴敏男，盛鐸，蔡壽昌，劉康懋，“數位式鎖相迴路”，中華民國專利發明第I245491 號，民國94年。