ECE2201/VDT2201: Electronic Devices-II
VLSI testing plays a pivotal role in ensuring the quality, reliability, and performance of integrated circuits. It is indispensable for addressing the challenges posed by the increasing complexity of designs, achieving cost-effective production, and meeting the stringent requirements of modern electronic applications.
This course is offered by the department of Electronics & Communication Engineering, Manipal University Jaipur, as a program elective course. The course is designed to prepare the students for jobs as DFT engineers in the industry. It targets the students interested in the domain of VLSI design to introduce them to the field of design for testability. The course covers techniques for efficient testing and the technique of automated test pattern generation and fault detection for digital circuits and memory. Students are expected to have background knowledge of digital electronics for better understanding of the course.
At the end of the course, students will be able to
Understand the concepts of VLSI testing and design for testability for Built-in Self-Test.
Apply the concepts fault modelling and collapsing for optimal fault coverage in digital circuits and memories.
Analyze various fault simulation and detection methods for digital circuits and memories.
Apply various test pattern generation methods for fault testing in digital circuits, memories.
Evaluate controllability and observability of digital circuits.
Evaluate different methods for test response compaction.
VLSI Testing and Testability play a pivotal role in ensuring the quality, reliability, and performance of integrated circuits. These processes are indispensable for addressing the challenges posed by the increasing complexity of designs, achieving cost-effective production, and meeting the stringent requirements of modern electronic applications.
This course is offered by Dept. of Electronics & Communication Engineering as a program elective Course. The course is mandatory for minor specialization in VLSI with an objective to prepare them for jobs as verification engineers in the industry. It targets the students interested in the domain of VLSI design to introduce them to the field of Design for Testability. The course covers techniques for efficient testing and the technique of automated test pattern generation and fault detection for digital circuits and memory. Students are expected to have background knowledge of Digital Electronics for better understanding of the course.
At the end of the course, students will be able to
Understand the concepts of VLSI testing and design for testability for Built-in Self-Test.
Apply the concepts fault modelling and collapsing for optimal fault coverage in digital circuits and memories.
Analyze various fault simulation and detection methods for digital circuits and memories.
Apply various test pattern generation methods for fault testing in digital circuits, memories.
Evaluate controllability and observability of digital circuits.
Evaluate different methods for test response compaction.
This course is offered by Dept. of Electronics & Communication Engineering as a Core theory course in IV semester of B. Tech. ECE as well as B.Tech. Electronics Engineering (VLSI Design and Technology) accompanying lab course. This course explores advanced electronic devices with a primary focus on FinFET technology, a cutting-edge development in the field of semiconductor devices. Students will delve into the principles governing traditional electronic devices, including PN junctions, JFETs, and MOSFETs, before immersing themselves in the intricate details of FinFETs. The course aims to provide students with an in-depth understanding of FinFET operation, its advantages, and its applications in contemporary electronic systems. Understanding of device physics and pn-junction is mandatory for better understanding of electrinic devices covered in this course.
At the end of the course, students will be able to :
Understand the principles of semiconductor physics as applied to advanced electronic devices
Analyze and describe the operation of traditional electronic devices such as PN junctions, JFETs, and MOSFETs.
Explore the principles and advantages of FinFET technology.
Design and analyze FinFET-based circuits for specific applications.
Evaluate the impact of FinFET technology on the development of advanced semiconductor devices.
This course is offered by Dept. of Electronics & Communication Engineering as a program elective Course. The course is mandatory for minor specialization in VLSI. It targets the students interested in VLSI design field. The course focuses on introducing CAD design issues that span the spectrum from circuit modelling with hardware description languages to cell-library binding while focussing on synthesis of design from high level language like C. It covers relevant mathematical topics followed by study of selective CAD problems and algorithms to solve these problems. This course will form the base for students to read, understand and analyse specialized books and research articles in this field. Students are expected to have elementary knowledge of HDL programming, MOS circuits and digital IC design for better understanding of the course.
At the end of the course, students will be able to :
Understand the requirements from a High-level Hardware Description Language (HDL) and CAD Tools to be able to achieve the best designs with the CAD tools
Make use of graph algorithms and Boolean algebra for VLSI Design Automation
Choose scheduling algorithms which underpin architectural level synthesis
Assess resource sharing and binding algorithms which underpin architectural level synthesis
Apply logic optimization for two-level and multiple level combinational and sequential circuits for user-defined constraints
Understand Timing Analysis and logical effort for MOS circuits
VLSI Physical Design has evolved as a complex specialization in VLSI and in-demand skill for the last 2 decades. The VLSI design cycle involves several steps including synthesis, floor plan, power plan, placement, clock tree synthesis, routing, static timing analysis, timing optimization and ends with delivering GDSII files to the foundry after doing all sign-off checks. This course will give decent exposure to physical design concepts, techniques. The student is expected to have basic concepts in digital circuit design.
At the end of the course, students will be able to :
Comprehend the goal, objective, and constraints of various phases of Physical Design Process
Apply graph theory in VLSI Physical Design process
Apply VLSI Physical design algorithms for circuit partitioning
Apply VLSI Physical design algorithms for circuit floorplanning and placement
Apply VLSI Physical design algorithms for circuit routing
Apply VLSI Physical design algorithms for layout generation and compaction