Dr. Kirti Gupta

Professor

Bharati Vidyapeeth's College of Engineering, New Delhi


  Dr. Kirti Gupta

   Professor 

  Vice Principal (Academics)

   Head, Department of Electronics and Communication Engineering

   Bharati Vidyapeeth’s College of Engineering

   A-4, Paschim Vihar,

   Delhi- 110063, India

   Email: kirtigupta22@gmail.com/ kirti.gupta@@bharatividyapeeth.edu          

   Phone: 011-25278444/25278443 (Ext-236), +91-9891349346

Granted Patents
 Granted an Indian patent on "A RACE-FREE CURRENT MODE LOGIC (NORA-CML) SYSTEM"  Patent no: 406525 dated: 13/09/22. 

Publications

 

·        Has published a total of 96 research papers in various International Journals and Conferences.

 

·        Has co-authored 02 books


Book Publications

 

Kirti Gupta,Neeta Pandey, Maneesha Gupta, “Model and Design of Improved Current Mode Logic Gates (Differential and Single-ended)” Spinger Nature, ISBN 978-981-15-0981-0 ISBN 978-981-15-0982-7 (eBook)

 

Riya Jain, Kirti Gupta, Neeta Pandey, “Dynamic Current Mode Logic: Concepts to Advancements” Lambart Academic Publishing, 2021, ISBN: 978-620-4-20810


 

List of Publications in Journal

 

1. Damyanti Singh, Kirti Gupta ,Neeta Pandey “A novel read decoupled 8T1M nvSRAM cell for near threshold operation” Elsevier, Microelectronics Journal, vol. 126, pp. 1-16, August 2022, (SCI/SCIE)

2. Ranjana Sivaram, Kirti Gupta, Neeta Pandey, “On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates, Microprocessors and Microsystems, Vol. 90, 1-6, 2022. (SCI/SCIE)

3. Monica Gupta, Kirti Gupta, Neeta Pandey, “A Novel PVT-variation tolerant Schmitt-trigger based 12T SRAM cell with improved write ability and high Ion/Ioff ratio in subthreshold region”, Wiley, International Journal of Circuit Theory and Application., 49, 2021. (SCI Journal with Impact Factor: 2.038) (SCI/SCIE)

4. Monica Gupta, Kirti Gupta, Neeta Pandey, “A Data‐Independent 9T SRAM Cell with Enhanced ION/IOFF Ratio and RBL Voltage Swing in Near Threshold and Sub‐Threshold Region”, Wiley, International Journal of Circuit Theory and Application., 49, 953-969, 2021. (SCI Journal with Impact Factor: 2.038) (SCI/SCIE)

5. Damyanti Singh, Kirti Gupta ,Neeta Pandey “A Novel Low-Power Nonvolatile 8T1M SRAM Cell” Arabian Journal for Science and Engineering (2021). https://doi.org/10.1007/s13369-021-06035-2 (SCI/SCIE)

6. Ranjana Sivaram, Kirti Gupta, Neeta Pandey, Neeta. “Impact of multi threshold transistor in positive feedback source coupled logic (PFSCL) fundamental cell” Analog Integrated Circuits & Signal Processing 109(2021) pp.173-185. (SCI/SCIE)

7. Monica Gupta, Kirti Gupta, Neeta Pandey, “Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm,” Microprocessors and Microsystems, Vol. 85, 1-19, 2021. (SCI/SCIE).

8. Monica Gupta, Kirti Gupta, Neeta Pandey, “ A data-independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub-threshold region” Wiley, International Journal of Circuit Theory and Application, 49, 953-969, Jan 2021. (SCI/SCIE)

9.    Riya Jain, Kirti Gupta, Neeta Pandey, “Hybrid Dynamic CML with Modified Current Source (H-MDyCML): A Low-Power Dynamic MCML Style” Advances in Electrical and Electronics Engineering, Vol. 19, March 2021.

10.  A survey of various wavelet-based image retrieval techniques and tuning of hyperparameters

11.  Kirti Gupta, Vishwas Gosain, Neeta Pandey, “Adiabatic Differential Cascode Voltage Switch Logic (A-DCVSL) for Low Power Applications”, Journal of King Saud University - Engineering Sciences, https://doi.org/10.1016/j.jksues.2020.09.018.

12.  Ranjana Sivaram, Kirti Gupta, Neeta Pandey, A new realization scheme for dynamic PFSCL style, vol 75, Nov 2020, pg: 169-177. https://doi.org/10.1016/j.vlsi.2020.05.004

13.  Prakhar Sharma, Shourya Gupta, Kirti Gupta, Neeta Pandey, “A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability,” Microelectronics Journal, vol. 97, 1-11, March 2020. (SCI/SCIE)

14.  Pratibha Bajpai, Neeta Pandey, Kirti Gupta, Jeebananda Panda, “LECTOR incorporated Differential Cascode Voltage Swing Logic (L-DCVSL),” in Springer, Analog Integrated Circuits and Signal Processing (Mixed signal letters), vol. 100 (1), 221-234, May 2019. (SCI/SCIE)

15.  Shourya Gupta, Kirti Gupta, Benton Calhoun, Neeta Pandey, “Low Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32nm CMOS,” IEEE Transactions on Circuits and Systems -I: Regular Papers, vol.66, n0.3, march 2019,978-988. (SCI/SCIE)

16.  Monica Gupta, Kirti Gupta, Neeta Pandey, ‘A Design of Low Leakage Cache Memory Cell for High Performance Processors,” Journal of Information and optimization sciences, vol. 40, no. 2, pp. 279-290, 2019.

17.  Sagar Jain, Shubham Garg, Neeta Pandey and Kirti Gupta, “Sinusoidal Power Clock based PFAL,” ICTACT Journal on Microelectronics, Oct-2019, Vol. 05, Issue: 03, pp: 801-806

18.  Shourya Gupta, Kirti Gupta, Neeta Pandey, “Pentavariate Vmin Analysis of A Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write And Divided Bit-Line Read,” IEEE Transactions on Circuits and Systems -I: Regular Papers, vol 65, no. 10, pp. 3326-3337, 2018. (SCI/SCIE)

19.  Shourya Gupta, Kirti Gupta, Neeta Pandey, “A 32nm Subthreshold 7T SRAM bit cell with Read Assist,” IEEE Transactions on VLSI systems, vol. 25, n0 12, pp.3473-3483, 2017. (SCI/SCIE)

20.  Pratibha Bajpai, Neeta Pandey, Kirti Gupta, Shrey Bagga, and Jeebananda Panda, “On Improving the Performance of Dynamic DCVSL Circuits,” Journal of Electrical and Computer Engineering, Article ID 8207104, vol. 2017, 11 pages, 2016. (SCI/SCIE)

21.  Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal, “New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies,” Journal of Circuits, Systems and Computers,, 1750186, 15 pages, 2017. (SCI/SCIE)

22.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Dynamic Positive-Feedback Source-Coupled Logic (D-PFSCL)” in Taylor and Francis, International Journal of Electronics, vol. 103, no.10, pp. 1626-1638, 2016. (SCI/SCIE)

23.  Neeta Pandey, Kirti Gupta, Bharat Choudhary, “New Proposal for MCML based Three-Input Logic Implementation,” VLSI Design, Article ID 8712768, vol. 2016, 10 pages, 2016. IF: 0.404.

24.  Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal, “Bus Implementation Using New Low Power PFSCL Tristate Buffers,” Active and Passive Electronic Component, Article ID 4517292, vol. 2016, 8 pages, 2016. (SCI/SCIE)

25.  Neeta Pandey, Damini Garg, Kirti Gupta, and Bharat Choudhary, “Hybrid Dynamic MCML style (H-DyCML): A High Speed Dynamic MCML style,” Journal of Engineering, Article ID 8027150, vol. 2016, 8 pages, 2016.

26.  Neeta Pandey, Kirti Gupta, Garima Bhatia, Bharat Choudhary, “MOS Current Mode Logic Exclusive-OR Gate using Multi-threshold Triple-tail Cells,” Elsevier, Microelectronics Journal, vol. 57, pp. 13-20, 2016. (SCI/SCIE)

27.  Nitish, Neeta Pandey, Kirti Gupta, Manu Kumar Saini, “DFAL based flexible multi-modulo prescaler,” ICTACT Journal on Microelectronics,  vol. 2, no. 3, pp. 273-280, 2014. (SCI/SCIE)

28.   Neeta Pandey, Kirti Gupta, Maneesha Gupta, “An Efficient Triple-tail Cell based PFSCL D-latch,” Elsevier, Microelectronics Journal, vol. 45, no. 8, pp. 1001-1007, 2014. (SCI/SCIE)

29.  Neeta Pandey, Kirti Gupta, Rajeshwari Pandey, Rishi Pandey, Tanvi Mittal, “Novel Oscillators in Subthreshold Regime;” International Journal of Electrical and Electronics Engineers vol. 6,no.2,pp.151-156, 2014.

30.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Analysis and Design of MOS Current Mode Logic Exclusive-OR Gate using Triple-tail Cells” Elsevier, Microelectronics Journal, vol. 44, no. 6, pp. 561-567, 2013. (SCI/SCIE)

31.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Low-power Tri-state Buffer in MOS Current Mode Logic,” in Springer, Analog Integrated Circuits and Signal Processing, vol. 75, no. 1, pp. 157-160, 2013. (SCI/SCIE)

32.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Low-Voltage MOS Current Mode Logic Multiplexer,” Radio Engineering, vol. 22, no. 1, 259-268, 2013. (SCI/SCIE)

33.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “MCML D-Latch Using Triple-Tail Cells: Analysis and Design,” Active and Passive Electronic Component, Article ID. 217674, vol. 2013, 9 pages, 2013. (SCI/SCIE)

34.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “MOS Current Mode Logic with Capacitive Coupling,” ISRN Electronics, Article ID 473257, vol. 2012, 7 pages, 2012.

35.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Multi-Threshold MOS Current Mode Logic based Asynchronous Pipeline Circuits,” ISRN Electronics, Article ID 529194, vol. 2012, 7 pages, 2012.

36.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “A Novel Active Shunt-Peaked MCML Array Multiplier,” vol. 6 no. 2, 2012.

37.  Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta, “New Low Power Tri-state Circuits in Positive Feedback Source Coupled Logic” in Journal of Electrical and Computer Engineering, Article ID 670508, vol. 2011, 6 pages, 2011. (SCI/SCIE)

38.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “A New Active Shunt-peaked MCML based High Performance 1:8 Demultiplexer for Serial Communication,” International Journal of Engineering and Technology, vol. 2, no. 10, pp: 4632-4639, 2010



 

List of Publications in Conference

 

1.    Mehul Madaan; Aniket Kumar; Shubham Kumar; Aniket Saha; Kirti Gupta, “Handwriting Generation and Synthesis: A Review”, 2022 Second International Conference on Power, Control and Computing Technologies (ICPC2T), March 2022, doi : 10.1109/ICPC2T53885.2022.9776932

2.    Damyanti Singh, Neeta Pandey, Kirti Gupta, “MS 8T1M nvSRAM Cell with Improved Write Performance”, 2022 International Mobile and Embedded Technology Conference (MECON), 2022, pp. 425-429, doi: 10.1109/MECON53876.2022.9752160.

3.    Gupta M, Gupta K, Pandey N, “A 22nm 10T FinFET SRAM Cell with Improved Read and Write performance in Sub-Threshold Region”, 8th International Conference on Signal Processing and Integrated Networks (SPIN), IEEE, pp. 452-457, Oct 2021.

4. Ranjana Sivaram, Kirti Gupta, Neeta Pandey, “Exploration of PFSCL in Subthreshold region of operation for use in ultra low power applications,” in 2nd International Conference of Emerging Technology (INCET 2021), India, 21st to 23rd May 2021

5. Ranjana Sivaram, Kirti Gupta, Neeta Pandey, “Power efficient architecture for PFSCL” 2021 International Conference on Emerging Trends in Industry 4.0 (ETI 4.0). Under publication in IEEE proceedings

6. Mayank Gaur, Mridul Arora, Varun Prakash, Yash Kumar, Kirti Gupta , Preeti Nagrath, "Analyzing Natural Language Essay Generator Models Using Long Short-Term Memory Neural Networks", International Conference on Innovative Computing and Communications, 20-21 February 2021

7. Varun Chopra, Akshita  Sharma, Jayant Nagpal, Tarun Lahrod, Paras Jain, Varun Srivastava, and Kirti Gupta, “A survey of various wavelet-based image retrieval techniques and tuning of hyper parameters” in 2nd Doctoral Symposium on Computational Intelligence (DoSCI-2021)-An International Conference (May 10, 2021).

8. Prakhar Sharma, Kirti Gupta, Neeta Pandey, “A Single-Ended 10-Transistors Static Random Access Memory Bit-Cell With Improved Write Margins at Low Voltages and High ION-IOFF Ratio,” 2019 International Conference on Smart Systems and Inventive Technology (ICSSIT), Tirunelveli, India, India, 27-29 Nov. 2019, ISBN: 978-1-7281-2119-2

9. Neeta Pandey ; Kirti Gupta ; Bharat Choudhary , “MCML Dynamic Register Design,” 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 582 – 586.

10.  Ranjana Sivaram ; Kirti Gupta ; Neeta Pandey, “New Improved Low Power Triple Tail Cell with Controlled Current Source” 2018 International Conference on Computing, Power and Communication Technologies (GUCON), Year: 2018. pp: 462 – 466.

11.  Parth Khatter ; Neeta Pandey , “An Arithmetic and Logical Unit using Reversible Gates” 2018 International Conference on Computing, Power and Communication Technologies (GUCON), Year: 2018, Pages: 476 - 480.

12.  Bhawna Rawat ; Kirti Gupta ; Nidhi Goel, “Low Voltage 7T SRAM cell in 32nm CMOS Technology Node” 2018 International Conference on Computing, Power and Communication Technologies (GUCON), Year: 2018, pp: 238 – 241.

13.  Bhawanand Jha, Kirti Gupta, Neeta Pandey, “Multiple Threshold CVSL Full Adder Design,” proceedings of the 13th  INDIACOM-INDIACOM 2019. pp. 1-5.

14.  Monica Gupta, Kirti Gupta, Neeta Pandey, “A 32-nm Sub-Threshold 9T SRAM Bitcell with Improved Read and Write performance,” IEEE International  Conference on Advances in  Computing, Communication  Control and  Networking(ICACCCN) , 12-13th Oct. 2018 .

15.  Sagar Jain ; Neeta Pandey ; Kirti Gupta, Complete Charge Recovery Diode Free Adiabatic Logic, 2018 5th International Conference on Signal Processing and Integrated Networks (SPIN), 2018, pp. 656 – 660.

16.  Vasudev Grover, Vishwas Gosain, Neeta Pandey and Kirti Gupta,” Arithmetic Logic Unit Using Diode Free Adiabatic Logic and Selection Unit for Adiabatic Logic Family”. in proceedings of in proceedings of IEEE International Conference on Signal Processing and Integrated Networks (SPIN), 2018

17.  Sivaram, Ranjana; Gupta, Kirti; Pandey, Neeta “Low power design for source coupled logic gates” 2018 15th IEEE India Council International Conference (INDICON), pp. 1-5.IEEE, 2018.

18.  Rahul Kumar Agrawal, Neeta Pandey, Kirti Gupta,  “Implementation of PFSCL Razor Flip flop,” In the proceedings of IEEE 2017 International Conference on “Computing Methodologies and Communication”, ICCMC, pp. 6-11.

19.  Utkarsh Mittal, Kirti Gupta, “On the Implementation of PFSCL Configurable Logic Block with High-Impedance State,” In the proceedings of International Conference on “Recent Innovations in Science, Agriculture, Engineering and Management” pp. 1157-1162.

20.  Kirti Gupta, Neeta Pandey, Naman Saxena, Shruti Dutta, “Implementation and Performance Comparison of a Four-Bit Ripple-Carry Adder Using Different MOS Current Mode Logic Topologies,” In the proceedings of International Conference on Computational Science and Its Applications – ICCSA 2017, pp. 299-313.

21.  Sourabh Singh, Kirti Gupta, “Data Encryption on FPGA using Huffman Coding,” In the proceedings of International Conference on “Recent Innovations in Science, Agriculture, Engineering and Management, pp: 1163-1168.

22.  Kirti Gupta. Neeta Pandey, “Analysis and Design of MOS Current Mode Logic Circuits with Active Inductor Load,” In the proceedings of 10th International Conference on Science, Technology and Management , pp. 291-300.

23.  Kirti Gupta, “Adiabatic logic for Ultra low power application,” 4th International Conference on Recent Advances in Engineering Science and Management   (ICRAESM-17), pp. 255-262.

24.  Akash Singh Rawat, Kirti Gupta, “Efficient 500 MHz Digital Phase Locked Loop Implementations in 180nm CMOS Technology,” In the proceedings of 10th International Conference on Science, Technology and Management , 311-320.

25.  Kartik Jain, Kirti Gupta, “An Ultra-low Voltage Hybrid OTA Based Low Pass Filter,” In the proceedings of 10th International Conference on Science, Technology and Management, pp. 306-310.

26.  Neeta Pandey, Kirti Gupta, Stuti Gupta, Suman Kumari, “MCML based Priority Encoders,” 4th International Conference on Recent Advances in Engineering Science and Management   (ICRAESM-17), 246-254.

27.  Shourya Gupta, Kirti Gupta and Neeta Pandey, “Stability Analysis of Different Dual-Port SRAM cells in Deep Submicron Region using N-Curve Method,” in proceedings of IEEE ICSC-2016, pp. 431-436.

28.  Kirti Gupta, Prayanshu Sharma and Neeta Pandey, “Design of low power subthreshold linear feedback shift register,” in proceedings of 1st IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems 2016, pp. 1-6.

29.  Kirti Gupta, Shrey Bagga and Neeta Pandey, “Efficient CVSL full adder realizations,” in proceedings of 1st IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems 2016, pp. 1-5.

30.  Shourya Gupta, Kirti Gupta, Neeta Pandey, “Performance Evaluation of SRAM cells for Deep Submicron Technologies,” Second International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity, pp. 292-296, 2016.

31.   Kirti Gupta, Pragati Shukla, Neeta Pandey, “ On the Implementation of PFSCL Adders,” Second International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity, pp. 287-291, 2016. 

32.   Gurashish, Ankit, Kirti Gupta, Neeta Pandey, “FPGA Implementation of different NRZ Line Coding Schemes,” IEEE India Inter National Conference on Information Processing, pp. 1-7, 2016.

33.  Neeta Pandey, Naman Saxena, Kirti Gupta, “Implementation of Asynchronous Pipeline using Transmission Gate logic”, in proceedings of IEEE International Conference on Computational Techniques in Information and Communication Technologies, ICCTICT, pp. 101-106, 2016.

34.  Neeta Pandey, Abhishek, Kirti Gupta, “PFSCL based Linear Feedback Shift Register”, in proceedings of IEEE International Conference on Computational Techniques in Information and Communication Technologies, ICCTICT, pp. 580-585, 2016.

35.  Neeta Pandey, Nitish, Kirti Gupta, “Pre-scalar for Diode Free Adiabatic Logic Family”, in proceedings of IEEE International Conference on Computational Techniques in Information and Communication Technologies, ICCTICT, pp. 481-485, 2016.

36.  Kirti Gupta, Utkarsh Mittal, Rahul Baghla, Pragati Shukla, Neeta Pandey, “On the Implementation of PFSCL Serializer,” in proceedings of in proceedings of IEEE International Conference on Signal Processing and Integrated Networks (SPIN), pp. 436-440, 2016.

37.  Kirti Gupta, Utkarsh Mittal, Rahul Baghla, Neeta Pandey, “Implementation of PFSCL based Demultiplexer,” in proceedings of IEEE International Conference on Computational Techniques in Information and Communication Technologies, ICCTICT, pp. 490-494, 2016.

38.  Samiksha Agarwal, Neeta Pandey, Kirti Gupta, Bharat Choudhary, “Design of MCML based LFSR for Low Power and Mixed Signal Applications,” in proceedings of Annual IEEE India International Conference INDICON, pp.1-6, 2015.

39.  Nitish, Neeta Pandey, Kirti Gupta, Rajeshwari Pandey, “DFAL based Implementation of Frequency Divider-by-3,” in proceedings of Annual IEEE India International Conference INDICON, pp.1-6, 2015.

40.  Neeta Pandey, Maneesha Gupta, Kirti Gupta, “A PFSCL based Configurable Logic Block,” in proceedings of Annual IEEE India International Conference INDICON, pp.1-4, 2015.

41.  Radhika, Neeta Pandey, Kirti Gupta, Maneesha Gupta, “Low Power D-latch Design using MCML Tri-state Buffers” in proceedings of IEEE International Conference on Signal Processing and Integrated Networks (SPIN), pp. 531 – 534, 2014.

42.  Neeta Pandey, Rashmi Pandey, Trisha Mittal, Kirti Gupta, “Ring and Coupled Ring oscillators in Subthreshold region,” in proceedings of International Conference on Signal Propagation and Computer technology, pp. 132-136, 2014.

43.  Himanshu Puri, Kshitij Ghai, Kirti Gupta, Neeta Pandey, “A Novel DFAL based Frequency Divider” in proceedings of IEEE International Conference on Signal Processing and Integrated Networks (SPIN), pp. 526 – 530, 2014.

44.  Himani Jawa, Kirti Gupta, “Novel Compressors in the Sub-threshold Regime”, in proceedings of IEEE International Conference on Signal Processing and Communication (ICSC), pp. 424 – 427, 2013.  

45.  Kirti Gupta, Radhika Tanwar, Neeta Pandey, Maneesha Gupta, “A Novel High Speed MCML Square Root Carry Select Adder for Mixed-Signal Applications” in proceedings of IEEE International Conference on Multimedia, Signal Processing and Communication Technologies, pp. 194-197, 2013.

46.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Performance Improvement of PFSCL Gates through Capacitive Coupling” in proceedings of IEEE International Conference on Multimedia, Signal Processing and Communication Technologies, pp.185-188, 2013.

47.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Low Power Multi-Threshold MOS Current Mode Logic Asynchronous Pipeline Circuits” in proceedings of IEEE 5th India International Conference on Power Electronics (IICPE), pp. 1-4, 2012.

48.  Kirti Gupta, Ranjana Sridhar, Neeta Pandey, Maneesha Gupta, “A New Improved Current Mode Logic Style with Feedback for Wireless Communication” in proceedings of Annual IEEE India Conference (INDICON), pp.1-4, 2011.

49.  Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta, “A New Current Mode Logic Style with Feedback for Digital Applications” in proceedings of IEEE International Conference on Multimedia, Signal Processing and Communication Technologies, pp. 164-167, 2011.

50.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “A Novel Active Shunt-Peaked MOS Current Mode Logic C-Element for Asynchronous Pipelines” in proceedings of IEEE International Conference on Multimedia, Signal Processing and Communication Technologies, pp. 122-125, 2011.

51.  Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta, “Performance Comparison of MCML and PFSCL Gates in 0.18μm CMOS Technology” in proceedings of IEEE International Conference on Computer and Communication Technology, pp. 230-233, 2011.

52.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Shunt-Peaking in MCML Memory Element Design in 0.18μm CMOS Technology” in proceedings of Annual IEEE India Conference (INDICON), pp. 1-4, 2010.

53.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “A Novel Active Shunt-Peaked MCML-based High Speed Four-Bit Ripple-Carry Adder” in proceedings of IEEE International Conference on Computer and Communication Technology, pp. 285-289, 2010.

54.  Kirti Gupta, Neeta Pandey, Maneesha Gupta, “Low power VLSI circuits for mobile wireless computing systems,” National Conference on Mobile Computing (MOBILE COMP-2008).

55.  Rahul Bahl, Kirti Gupta, “Insurance Information Warehouse,” National Conference on Future Trends in Information Technology (FIT- 2005).

56.  M.K. Raina, Kirti Gupta, Yogita Arora, “Electromagnetic Interference Compatibility for Mobile Communication System, URSI, General Assembly, Time and Frequency section, National Physical Laboratory, 2005.




Consultancy

 

š Consultancy Programme in VLSI Design for Connexant, Noida in June 2006

 

š Consultancy Programme in VLSI Design for nSys Design Systems Pvt. Ltd., New Delhi in June 2006, June 2007, June 2008.

 

Skill Set

 

š Languages Known:  PSPICE

š Simulators used: Cadence Virtuoso; Mentor Graphics HEP2; Microwind; Orcad PSPICE, Tanner Tool, SYMICA

 

Achievements

š Served as a reviewer for 

IEEE Transaction on Very Large Scale Integration Systems; 

IEEE Transaction on Circuits and Systems-I, 

Taylor and Francis, International Journal of Electronics; 

Elsevier, International Journal of Electronics and Communications, 

Microelectronics Journal, 

VLSI Integration

Microprocessor and Microsystems

 

š Gate 2002 Qualified

 

š Awarded Certificate of Merit by CBSE for being in the top 0.1 percent of successful candidate of AISSCE 1998 in physics.

 

š Awarded Merit Certificate by Govt. of NCT of Delhi under National Scholarship Scheme.

 

š Served as Convenor in AICTE registered Institute Innovation Council, 2018-2019

 

 

Workshops & STTPs

š Participated in AICTE-ISTE sponsored two week short term course on "Fuzzy Logic & Neural Networks in Identification & Control of Non-linear Systems", held at NSIT, New Delhi, Dec, 2003 - Jan 2004

 

š Participated in workshop titled “2005 Xilinx University Workshop”, held at NSIT, New Delhi in association with CG-Corel, 26th – 29th July, 2005.

 

š Participated in National Level Workshop on "Current Trends in CAD Tools for VLSI Design" held at CDAC, Noida, 12th April 2007.

 

š Participated in the UGC workshop on “Capacity building for Women Managers in Higher Education” held at Dept. of Electrical Engineering, Jamia Millia Islamia, New Delhi, 13th – 18th Nov, 2006.

 

š Participated in one week AICTE-ISTE sponsored short term course on Nanotechnology held at NSIT, New Delhi, 16th – 20th June, 2008.

 

š Participated in GIAN course on “Circuits, Microsystems and packaging techniques intended for autonomous brain-machine interface” in DTU, 20th- 24th December 2016.

 

š Completed 12 weeks NPTEL course on Intellectual Property, IIT, Madras, July-Oct 2018

 

š Participated in one week FDP on “Outcome based Education (OBE) and NBA Accreditation process” held at BVICAM, New Delhi, 23-27 November 2020.

 

š Participated in one week short term training program on “Emerging Nanoscale Devices, Circuits and Its Applications (NANODC- 21)” organized by Department of Electronics & Communication Engineering, Delhi Technological University, Delhi, India , 10-14May,2021.

 

š Participated and completed successfully AICTE Training And Learning (ATAL) Academy Online Elementary FDP on "Recent Advances in VLSI Design and System" from 22/11/2021 to 26/11/2021 at Dharmsinh Desai University, Nadiad.

 

š Participated and completed successfully AICTE Training And Learning (ATAL) Academy Online Elementary FDP on "VLSI Design Techniques and its Applications in AI/ML" from 15/11/2021 to 19/11/2021 at Thapar Institute of Engineering & Technology, Patiala.